purpose of OE pin in Altera MAX CPLD

[shaiko]

Hello,

What is the purpose of the OE1 and OE2 pins in ALTERA MAX3000 CPLD ?
https://www.altera.com/literature/ds/m3000a.pdf
(page 5)

 

[FvM]

It's an option to implement global output enable for an arbitrary selection of pins without consuming additional macro cells.

 

[shaiko]

Why 2 pins? How many outputs does each pin control ?
If I drive OE1 to VCC what will it do?
If I drive OE2 to VCC what will it do?

If you look at the pin description you'll see that OE2 can also be a clock input.
How do I decide if the pin functions as an output enable or as a global clock ?

 

[FvM]

The pin will get a function according to your design. The said dedicated OE function is an option that can be utilized by the design compiler, if you select the pins respectively. Otherwise it's ignored.

 

[shaiko]

Another question,
Is this device has an internal POR circuit ?

 

[FvM]

POR is mentioned in the datasheet. As far as I remember it involves a reset of all registers.

 

[shaiko]

Yes,
But it doesn't mention that the POR circuitry is internal...

 

[FvM]

The term POR always implies an automatical (internal) reset circuit. So does the below quoted datasheet statement. It doesn't explicitely speak of register initialization, however.

The POR time for all MAX 3000A devices does not exceed 100 µs. The sufficient VCCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.

 

[shaiko]

The term POR always implies an automatical (internal) reset circuit.

This isn't accurate.
Many companies manufacture reset generators (external IC) and call them POR.
For example:
**broken link removed**

 

[FvM]

This isn't accurate.

What has the stament to do with accuracy? The question was about POR as chip feature. There are two options, to cause a chip reset on power on:
- it's generated internally, as in the present case. That's what you call a built-in POR feature.
- you operate a reset input of the chip at power on. From the chips perspective, the respective pin is just a general reset input, the term POR won't be found in the chip's datasheet related to it.

 

[shaiko]

So...the internal POR generator is ORed with the GCLRn external signal ?

 

[FvM]

So...the internal POR generator is ORed with the GCLRn external signal ?

Yes, if GCLRn is used at all. I must say, that I didn't check the exact behavoiur with MAX3000, I have very few projects using this device. But the same behaviour is implemented with all programmable logic devices (FPGA and CPLD) I know.

 

[shaiko]

It's also my first time with the MAX3000A.
The customer insisted on a 5V tolerant device.

The reason I asked about the existence of an internal POR for this particular device is because of a questionable statement made by the local Altera FAE:

"Only our SRAM devices have an internal POR generator. The EEPROM CPLDs don't have an internal POR and will have to be fitted with an external POR IC that connects to the GCLRn pin".

I was VERY doubtful about the above and decided to ask here.

 

[FvM]

I guess, there's a least a difference that FPGAs have a voltage threshold detector and also a longer POR time intervall > ms. They mainly need it to assure reliable configuration load under all circumstances.

If you want the POR to achieve a defined state of synchronous logic, e.g. a FSM, also an external POR isn't sufficient. You need to release the reset synchronous to the clock