Pulse through capacitor

[nnayak82]

Hi folks
I have a pulse source and I am feeding it to a capacitor designed to pass the pulse unattenuated and undistorted. The base line of the pulse from pulse generator is 0Volts .But the baseline of the pulse at the other end of capacitor [i.e. at the output] is non zero.

Can anyone explain the reason ?

 

[FvM]

The purpose of the capacitor isn't clear from your post. In my opinion, a capacitor would be only useful, if a DC voltage difference has to be spanned.

I understand, that the baseline on the circuit side is changing during the pulse. A change according to the current integral or "charge" of the pulse has to be expected however:

ΔV = 1/C∫I(t)dt

 

[albbg]

You can see the capacitor as a DC removal device. This means the output of the capacitor will be a signal with zero volt average (that is the DC component) regardless the average of the input signal.

 

[dick_freebird]

So there's a DC bias on the other side. What's the problem?

 

[LvW]

As far as I understand the question from nnayak82, he has no problem but he wants to know the REASON for the described phenomenon.
Here is my answer which is rather simple: The pulse series between 0 and Vmax volts has, of course, a mean value (Vmax/2 for a duty cycle of 1:1).
This mean value which is identical to the dc component of the corresponding FOURIER series cannot pass the capacitor (in the steady state!) in contrast to all other FOURIER components (which are ac). Thus, the signal after passing the capacitor is a pulse series without a dc component (between -Vmax/2 and +Vmax/2).

 

[nnayak82]

Thanks for the replies guys .Well I'll frame my query like this ::

I am designing a bias tee circuit where I'll be giving in a pulse at one port, dc at other and from the third port I'll get RF+DC . I am feeding pulses at 50Khz with 100ns pulse width and the designed bias tee works fine. The designed bias tee is as shown in attached .pdf file.
What I observed is when I feed the pulses [having 0 base line] from pulse generator into port labeled RF , the pulses coming out from RF+DC port has NON ZERO baseline. Now this is the case even if we do not apply DC at the DC port.

 

[nnayak82]

My question is
Why should the baseline vary ?

---------- Post added at 07:25 ---------- Previous post was at 07:17 ----------

Now , The way I have corrected for the baseline is as follows :

Step1] I calculate Average value of pulse
Step2] Depending on the sign of the average value I add/subtract it from DC bias .

Example: If the average value of pulse is 0.05Volts , the baseline shifts by 0.05Volts.Hence I subtract 0.05Volts from DC bias to obtain baseline at ZERO.

Now ,
I think the reason for baseline shift is:
Capacitor will block the dc and hence average value of dc at RF+DC port is zero[Assuming NO DC is applied]
Hence as pointed out by LvW in his above post the pulse at the RF+DC port will be without AVERAGE DC Value for which we need to correct . Am I right ?

 

[albbg]

From your circuit in input you have a train of pulses from 0 to 10V of width 100ns every 100us (the output voltage is divided by 2). The input DC component is then
Vin(DC) = (10*100ns+0*99.9us)/100us = 10mV since after the capacitor no DC can be present (of course if SRC2 is disconnetted) then must be:
Vout(DC) = (5*100ns+Offest*99.9us)/100us = 0
from which we can calculate Offset = -5*100ns/99.9us = -5mV this means the output baseline will start from a value of -5mV to reach 10V. However the baseline will not be an horizontal line since the period is very long with respect to the capacitor value, so you will se a capacitor charge with a mean value of -5mV. When you will connect SRC2 (5V battery) I expect an output signal going from 4.99V to 10V.

 

[nnayak82]

@albbg
thanks for ur reply
Vout(DC) should be 0 Volts [understood]

but i did not understand

Vout(DC) = (5*100ns+Offest*99.9us)/100us


Also I did not get why is the circuit divide by 2

Lets do one thing ....lets keep it simple [for my understanding] by disconnecting the inductor
could you please analyze it now ?

 

[nnayak82]

@albbg
With all due respect
I think u have made a slight mistake here.
When a pulse source[source impedance 50ohm] is 50ohm terminated , the voltage for which it is set is the voltage drop across the 50ohm load resistance .This implies the internal circuitry of pulse generator produces twice the voltage it is set for.

 

[FvM]

the voltage for which it is set is the voltage drop across the 50ohm load resistance

Would be true for e.g. a signal generator with internal 50 ohm termination, and also for some circuit simulator RF sources. I understand that you are referring to your ADS simulation circuit. The VtPulse source obviously has no internal series termination and is specified by it's internal source voltage.