anee_anil
Newbie level 4
frequency and pulse width generator in vhdl
Hi all,
I'm trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse derived from a 80Mhz clock.
The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.
The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width
and there will be 6 bit input, through which we can select 8 output ports.
when we select other signal, the previous signal should retain the data.
entity pulse_gen is
port(clk : in std_logic;
freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);
wave_sel : in std_logic_vector(5 downto 0);
out_wave : out std_logic_vector(7 downto 0));
end entity;
Hi all,
I'm trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse derived from a 80Mhz clock.
The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.
The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width
and there will be 6 bit input, through which we can select 8 output ports.
when we select other signal, the previous signal should retain the data.
entity pulse_gen is
port(clk : in std_logic;
freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);
wave_sel : in std_logic_vector(5 downto 0);
out_wave : out std_logic_vector(7 downto 0));
end entity;