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pulse generator in vhdl

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anee_anil

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frequency and pulse width generator in vhdl

Hi all,

I'm trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse derived from a 80Mhz clock.

The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.

The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width

and there will be 6 bit input, through which we can select 8 output ports.
when we select other signal, the previous signal should retain the data.


entity pulse_gen is
port(clk : in std_logic;
freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);
wave_sel : in std_logic_vector(5 downto 0);
out_wave : out std_logic_vector(7 downto 0));
end entity;
 

anee_anil

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pulse width generator

Hi,
This is pulse repetition time(PRT or PRF) and pulse width generation.
Please anyone able to code for it?

With regards
 

anee_anil

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std_logic_vector pulse

Hi all,
I have coded for pulse repetition and pulse width generator.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulse_generator is
port(clk : in std_logic;
prt : in std_logic_vector(15 downto 0);
pw : in std_logic_vector(9 downto 0); -- pulse width
wave_sel : in std_logic_vector(5 downto 0);
out_wave0,out_wave1,out_wave2,out_wave3,out_wave4,out_wave5,out_wave6,out_wave7 : out std_logic);
end pulse_generator;

architecture Behavioral of pulse_generator is
signal count2 : std_logic_vector(9 downto 0) :="0000000000";
signal count1 : std_logic_vector(15 downto 0) :="0000000000000000";
signal clkouta, clkout1, clkout2,clkoutb,clkoutc,clkoutd,clkoute,clkoutf,clkoutg,clkouth : std_logic;
begin
process(clk)
begin
case wave_sel is
when "000000" => out_wave0 <= clkouta;
when "000001" => out_wave1 <= clkoutb;
when "000010" => out_wave2 <= clkoutc;
when "000011" => out_wave3 <= clkoutd;
when "000100" => out_wave4 <= clkoute;
when "000101" => out_wave5 <= clkoutf;
when "000110" => out_wave6 <= clkoutg;
when "000111" => out_wave7 <= clkouth;
when others => null;
end case;
end process;

------------------------out_wave(0)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkouta <= clkout1 and clkout2;
end process;
----------------------------------------------------------------------
------------------------out_wave(1)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoutb <= clkout1 and clkout2;
end process;
---------------------------------------------------------------------------------
------------------------out_wave(2)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoutc <= clkout1 and clkout2;
end process;
---------------------------------------------------------------------------------
------------------------out_wave(3)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoutd <= clkout1 and clkout2;
end process;
----------------------------------------------------------------------
------------------------out_wave(4)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoute <= clkout1 and clkout2;
end process;
---------------------------------------------------------------------------------
------------------------out_wave(5)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoutf <= clkout1 and clkout2;
end process;
---------------------------------------------------------------------------------
------------------------out_wave(6)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkoutg <= clkout1 and clkout2;
end process;
----------------------------------------------------------------------
------------------------out_wave(7)------------------------------------
process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 : std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkouth <= clkout1 and clkout2;
end process;
---------------------------------------------------------------------------------
end Behavioral;


PRT value specifies the number of clock cycles after which the wave repeats. PW value specifies the number of clock cycles for which the pulse width should remain high.

Please anybody help me to code like
Once the wave is assigned to the signal, it should retain the same PRT and pulse width even after the output wave is changed and the changed wave should have new PRT and PW.


Thanks with regards
ANIL
 

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