Pullup/pulldown resistor confusion

[nicky.r]

Hello,

I have a 3.3v LVTTL tristate output which has a 4.7k pullup resistor to 3.3v. This line is connected to a 3.3vLVTTL input which has a pull down resistor of 1k.Will this output be able to drive a low level and a high level to the input correctly? i.e. will the input recognise a low output as a low level and a high output as a high level?

Thank you

 

[FvM]

I have a 3.3v LVTTL tristate output which has a 4.7k pullup resistor to 3.3v. This line is connected to a 3.3vLVTTL input which has a pull down resistor of 1k.

Why? You shouldn't do that.

Will this output be able to drive a low level and a high level to the input correctly? i.e. will the input recognise a low output as a low level and a high output as a high level?

Depends on the logic family and respective drive strength. Low state will be easy, high should work in most cases.

 

[alexan_e]

The 4.7K pullup is used only when the output is in tristate.
When the output has a forced value then the pullup doesn't matter, the output voltage is provided with the internal output circuit (mosfet or transistor) which can drive loads as specified in the datasheet (1K shouldn't be a problem).
When the tristate is enabled then you will probably have about 3v3 * 1k/(4k7+1k) = 0.58v because the output pull up and input pull down form a voltage divider, this should be detected as low in the input since it it below 0.8v

Alex

 

[nicky.r]

Thank you for your reply.I was working with a chip that has one pull-up output pin and a pull down input pin and these to pins were to be connected to test a particular application.

---------- Post added at 09:47 ---------- Previous post was at 09:35 ----------

Thanks for your reply.Could you please tell me whether if i have a 10k pull-down 3.3v lvttl pin and I give a high(3.3v) to this pin,will it be recognised as a high.I am not sure of the input impedance of the pin.I am having some difficulty finding the LVTTL characteristics.I have JESDBC-01 doc.

 

[FvM]

As mentioned before, modern logic families have additional drive strength specifications. LVTTL is specifying the voltage levels. Having an internal 10k pull-down suggests CMOS logic, so no additional input currents will be present. Any LVTTL output, even with lowest drive strength, is able to drive a 10 K resistor.