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Pull down resistors are used for and unused inputs for CMOS

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I see pull up resistors often but I don't see pull down resistor much. When are pull down resistors used mostly. I have only seen pull down resistors used in ECL logic circuits. Rarely do I see pull down resistors in TTL and CMOS circuits.

When unused CMOS input pins are tied to +VCC or ground does it make a difference if the unused pins are tied to +VCC or ground. Does tied unused pins to +VCC draw more current from the power supply?
 

KlausST

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Hi,

in most cases it is not important wheter to use pullup or pulldown. Even the current consumption is often negligible.
Reading the datasheets will give you detailed information.

For sure there are functional considerations when to pullup or pulldown.
Obviously unused inputs on a AND gate should be pulled up. And unused gates of OR gates shuld be pulled down.
The same is obvious for unused RESET, ENABLE, DISABLE, POWERDOWN, OUTPUT ENABLE or other pins with dedicated function.

Another point of view is the validity of data.
If a transmitter sends out a LOW as active level, then the receiver does not know wether it is a true "active" value or the transmitter is powered off.

Klaus
 

pjmelect

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On TTL you should use a pull up resistor because of power considerations, on CMOS it does not matter if you use a pull up or pull down, but pull up is often used because of the standard set by TTL. (this is assuming that pull up or down does not effect the logic or other considerations)
 

Audioguru

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When unused CMOS input pins are tied to +VCC or ground does it make a difference if the unused pins are tied to +VCC or ground?
Of course it makes a difference. When you learn about digital logic then you will see that when the inputs states of a logic device are high or is low then the output state is determined.

Does tied unused pins to +VCC (or ground) draw more current from the power supply?
When you learn about Cmos logic and read a Cmos datasheet then you will see that it makes no difference because the supply current of an unloaded Cmos logic device is almost nothing when its inputs are high or low.
 

hobbyckts

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its depends about the logic output of that particular pin. If the pin is active low need to always pulled-up and if it is active high then need to pulled down
 

Audioguru

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its depends about the logic output of that particular pin. If the pin is active low need to always pulled-up and if it is active high then need to pulled down
Don't you mean to say " the logic input" of that particular pin? You do not want to short an active output.
 

chemelec

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For the 4000 Series of CMos IC's, It is usually Recommended to Ground, UNUSED INPUT PINS.
And the Output Pins are left Open, with No Connections to them.
 

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For the 4000 Series of CMos IC's, It is usually Recommended to Ground, UNUSED INPUT PINS.
That will not work if you have an AND or NAND gate because if any one (or more) input is low then the output locks up.
An example is when a CD4011 two inputs NAND gate is used as an inverter. The unused input must be high because if it is low then the output will always be high.
 

xenos

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That will not work if you have an AND or NAND gate because if any one (or more) input is low then the output locks up.
An example is when a CD4011 two inputs NAND gate is used as an inverter. The unused input must be high because if it is low then the output will always be high.

If you want to use a NAND or a NOT gate to produce an other type of gate, then none of this specific gate input pins, is unused! They have specific level to be tied on.

What chemelec said, is true.
 

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An unused input on an AND or NAND gate must be high (not grounded) or the gate or resulting inverter (NOT gate?) will not work.
 

xenos

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An unused input on an AND or NAND gate must be high (not grounded) or the gate or resulting inverter (NOT gate?) will not work.

There are NO unused input pins, on ANY used gate. If someone lefts an input of a used gate unconnected, he obvious do not undertand IC logic.

Obviously we say the same, but with different terminology.
 

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There are NO unused input pins, on ANY used gate.
You are wrong.
Think about needing an inverter or a two input AND or NAND gate but you have only a three input gate available. Then the unused input must be connected high for it to work. If the unused input is wrongly connected to ground then the inverter or two input gate will not work.
 

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NAND3 with I0, I1, I2 and output O

To make an inverter...


Code Verilog - [expand]
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module inv (
  output o,
  input  i
);
nand3  nand3_inst (
  .O  (o)
  .I0 (i),
  .I1 (i),
  .I2 (i)
);
endmodule

 

chemelec

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You Misunderstood What I Wrote in #7.

And the Output Pins are left Open, with No Connections to them.

My Explaination is for When a Section of the IC is NOT in Use!
 

KlausST

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Hi,

CD4012 is a dual 4 input NAND gate.

each gate has A, B, C, D, as inputs and Y as output.

If you need only 3 of the 4 inputs (of one gate) you have to pull up the fourth input. If you GROUND the unused input, then output is always HIGH, what makes the gate useless.

Klaus
 

chemelec

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Your Not Understanding What I am Saying!

I SAID: When the OUTPUT Is NOT CONNECTED to anything.
So as an Example: When your Only using 1/2 of the 4012, the other UNUSED Half can have its input pins Grounded.
 

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