I agree with Klaus, confirm with Atmel as I could not find in datasheet
adequate description of power up effects on GPIO.
Typically a field engineer (FAE) would be a good contact point, or a post
on Atmel web site.
Power sequencing is not a trivial design consideration, one can get some
pretty strange behavior in circuits not designed for this, as well as outright
device failure. True for both power up and power down.
I ran across another datasheet recently that stated GPIO was in tri-state on
power up. What was not stated was that for all chip Vdd voltages ? In fact
it was not, eg. GPIO was indeterminate at voltages below chip operating specs.
If your chip drives into a bipolar transistor for power switching, like relays, etc..,
say an NPN, it turns on at 1 Vbe, in fact its on partially << Vbe. So a 3.3V chip with
transients at levels of a Vbe as its power ramps up can cause premature Relay
turn on. Good datasheets cover this. Some do not.
A common approach is to use, in the above case, a pulldown R. The trade off
here is too low a pulldown reduces operating noise margin, too high not enough
reduction in transient amplitude. And leakage absorption issues where leakage
thru the R can turn on an external device. choose carefully.
Regards, Dana.