PTM FinFet models with hspice - current flows even with no voltage source

[3pitom3]

I've been using >=22nm PTM models for a few months now, and it's been going pretty well.
Now I wanted to try newer technologies, which are FinFet-based, for example 20nm HP.

Unfortunately I'm getting some behavior that I'm not sure I can explain.

Attached is a simple hspice deck that sets each port of the transistor to 0V.
If I set the 'use_finfets' parameter to 0, it uses 22nm LP technology, and as expected, returns:

**** voltage sources

subckt
element 0:vdrain 0:vgate 0:vsource
volts 0. 0. 0.
current 0. 0. 0.
power 0. 0. 0.

There's no voltage being applied anywhere, so nothing happens, and this is true whether I use an nmos or a pmos
(set with the 'use_n' parameter).

Now if I set 'use_finfets' to 1, it uses 20nm HP technology (FinFet), and returns this:

**** voltage sources

subckt
element 0:vdrain 0:vgate 0:vsource
volts 0. 0. 0.
current 2.211e-19 -4.422e-19 2.211e-19
power 0. 0. 0.

There's current flowing through the voltage sources?? I'm not sure I can explain why.

Also, if I set 'use_n' to 1 (to use a PMOS instead of an NMOS), it returns:

subckt
element 0:vdrain 0:vgate 0:vsource
volts 0. 0. 0.
current -1.118e-22 2.237e-22 -1.118e-22
power 0. 0. 0.

So again, current flows, but this time it flows in the opposite direction??

Thank you for your help!

The archive contains test2.sp, the spice deck, as well as the PTM models found here: http://ptm.asu.edu/latest.html

test2.sp is as follows:

* Test FinFet
.param use_finfets=1
.param use_n=1
.param Vol = 0.70
.param simt = 5n
.param fin_height=28n
.param fin_width=15n
.param lg=24n
.if (use_finfets == 1)
	.include "20nm_HP.pm"
	.param tech = 20e-9

        .subckt pfetz drain gate source body wsize=1 lsize=1
                mpfet drain gate source body pfet L='lsize*lg' NFIN=wsize
        .ends
        .subckt nfetz drain gate source body wsize=1 lsize=1
                mnfet drain gate source body nfet L='lsize*lg' NFIN=wsize
        .ends

.else
	.include "22nm_HP.pm"
	.param tech = 22e-9

        .subckt pfetz drain gate source body wsize=1 lsize=1
                M1 drain gate source body pmos L='lsize*tech' W='wsize*tech'
        .ends
        .subckt nfetz drain gate source body wsize=1 lsize=1
                M1 drain gate source body nmos L='lsize*tech' W='wsize*tech'
        .ends
.endif
Vgate gate 0 0
Vdrain drain 0 0
Vsource source 0 0
.if (use_n == 0)
	X1 source gate drain 0 nfetz
.else
	X1 source gate drain 0 pfetz
.endif
.TEMP 85
.OP
.OPTIONS NODE
.tran 'simt/100' simt
.end

 

[erikl]

... There's current flowing through the voltage sources??

.param Vol = 0.70

May be this voltage parameter is the culprit.

Also, if I set 'use_n' to 1 (to use a PMOS instead of an NMOS), it returns:
So again, current flows, but this time it flows in the opposite direction??

This is normal for PMOS as against NMOS.

 

[3pitom3]

Thanks for your answer!
".param Vol = 0.70" isn't actually used, I can remove that line and the same still happens.

 

[dick_freebird]

So maybe the fancier model has gate tunneling current
(from the look of it, the S & D sum to equal the gate).

 

[erikl]

".param Vol = 0.70" isn't actually used, I can remove that line and the same still happens.

If these 20nm HP technology FinFETs use a similar SPICE setup as the PTM SPICE files for 32nm, if not given, Vol will be calculated within a subcircuit (in a relatively complex manner, s. below) and used anyway:

---

Code PHP (brief) - [expand]
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.subckt DGNMOS NVd NVgf NVgb NVs wdg=80n ldg=32n
 
En1 NVgf NVgf1 VOL = 'nlambda1*(-1*N*Vt*log(1+exp((((nlambda2*(npvthb0-(v(NVd)-v(NVs))*delta2)+(npvthf0-(v(NVd)-v(NVs))*delta1))/(1-(nlambda1*nlambda2))+Voff2)-(v(NVgb)-v(NVs))-Voff1)/N/Vt))+N*Vt*log(1+exp((((nlambda2*(npvthb0-(v(NVd)-v(NVs))*delta2)+(npvthf0-(v(NVd)-v(NVs))*delta1))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))-1*N*Vt*log(1+exp(((-1)*((nlambda2*(npvthb0-(v(NVd)-v(NVs))*delta2)+(npvthf0-(v(NVd)-v(NVs))*delta1))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))+N*Vt*log(1+exp((-Voff1)/N/Vt)))'
En2 NVgb NVgb1 VOL = 'nlambda2*(-1*N*Vt*log(1+exp((((nlambda1*(npvthf0-(v(NVd)-v(NVs))*delta1)+(npvthb0-(v(NVd)-v(NVs))*delta2))/(1-(nlambda1*nlambda2))+Voff2)-(v(NVgf)-v(NVs))-Voff1)/N/Vt))+N*Vt*log(1+exp((((nlambda1*(npvthf0-(v(NVd)-v(NVs))*delta1)+(npvthb0-(v(NVd)-v(NVs))*delta2))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))-1*N*Vt*log(1+exp(((-1)*((nlambda1*(npvthf0-(v(NVd)-v(NVs))*delta1)+(npvthb0-(v(NVd)-v(NVs))*delta2))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))+N*Vt*log(1+exp((-Voff1)/N/Vt)))'
...
mn1  NVd  NVgf1 NVs  0  nmos1 w='wdg/2' l='ldg'
...
mn2  NVd  NVgb1 NVs  0  nmos2 w='wdg/2' l='ldg'
...
.ends

---

If this is the case, you should explicitly set Vol = 0 , if you want to see if this is the reason for the currents.

 

[3pitom3]

I just tried explicitly setting Vol=0, the currents are still there.
I guess it could be gate tunneling current that wasn't modeled in the non-FinFet models...

 

[erikl]

I just tried explicitly setting Vol=0, the currents are still there.
I guess it could be gate tunneling current ...

Vgate gate 0 0
Vdrain drain 0 0
Vsource source 0 0

But doesn't even a tunnel current need a voltage source? Very strange.

 

[dick_freebird]

These currents are very low and probably within tolerances.
Maybe the tunneling current (if) feature just gives it a new
thing to dither about, and it coughs up a "good enough" (but
not zero, as you'd expect / like) answer.

I'd be curious what consistency is seen, if you had multiple
instances of this finfet in some disorderly topology.

You might drill to the bottom of the subcircuit / model
pile and see what you see. In the past I have found some
foundry models for SOI that used arbitrary and large
voltages to back-bias the (allegedly missing, though
practically not quite) body to "put it out of play" in RF
switch applications, and they dummied out all of the
S-B, D-B diode params "well enough". If you're exclusively
interested in 50-ohm systems, that is. When I came in
and started using these models for low power analog,
"mystery currents" from nowhere, to the source and drain,
appeared at high temp where the "dummied" diodes had
enough reverse conduction to make some absurd results.

Finfets are an SOI method, and new enough to not have
a righteous standard compact model of their own, so I
would say some shenanigans of this sort can't be ruled out.


So see if you can find voltage sources or behavioral
equivalents somewhere down in the modeling hierarchy,
that make the top level Vxy=0 condition, something
else at the lowest level.

And of course if this finfet is really a veriloga or something,
then assume nothing.

 

[3pitom3]

Thanks for you reply. I'll let you know if I find something.