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pt timing problem! urgently

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rickyice

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pt timing

Please reference the following for the next group of questions

Startpoint: fifo_rd_pd_reg_16_
(rising edge-triggered flip-flop clocked by my_clock)
Endpoint: we_bank_0_reg_2_
(rising edge-triggered flip-flop clocked by my_clock)
Path Group: my_group
Path Type: max


Point Cap Trans Incr Path
------------------------------------------------------------------------------------
clock my_clock (rise edge) 0.0000 0.0000
clock network delay (ideal) 0.0000 0.0000
fifo_rd_pd_reg_16_/CK (p_SDFFHX4) 0.0000 0.0000 0.0000 r
fifo_rd_pd_reg_16_/Q (p_SDFFHX4) 0.0226 0.0542 0.1166 0.1166 f
obuf_U1904/Y (NAND3BX4) 0.0095 0.0643 0.0915 0.2082 f
obuf_U1903/Y (INVX8) 0.0188 0.0450 0.0385 0.2467 r
obuf_buf_1_add_524_U14/Y (NAND2X4) 0.0088 0.0431 0.0374 0.2841 f
U7015/Y (OAI21X4) 0.0111 0.1008 0.0781 0.3622 r
U22745/Y (AOI21X4) 0.0054 0.0481 0.0294 0.3916 f
obuf_U9743/Y (OAI21X4) 0.0067 0.0772 0.0638 0.4554 r
obuf_buf_1_add_524_U57/Y (XNOR2X4) 0.0098 0.1071 0.0769 0.5323 r
DP_OP_248_5346_8_U51/CO0 (AFCSHCINX2) 0.0037 0.0970 0.1378 0.6702 r
obuf_U9662/Y (MX2X4) 0.0077 0.0382 0.0825 0.7527 r
DP_OP_248_5346_8_U44/S (AFCSHCINX4) 0.0075 0.0462 0.1200 0.8726 f
obuf_U9746/Y (INVX6) 0.0174 0.0463 0.0394 0.9120 r
obuf_U1772/Y (NOR2X4) 0.0113 0.0554 0.0294 0.9414 f
U17999/Y (OA22X4) 0.0058 0.0398 0.1128 1.0542 f
obuf_U1852/Y (NOR2X4) 0.0116 0.0909 0.0686 1.1228 r
U26782/Y (INVX10) 0.0549 0.0558 0.0538 1.1765 f
U7011/Y (OA22X4) 0.0092 0.0465 0.0982 1.2747 f
U27252/Y (CLKNAND2X2) 0.0057 0.0484 0.0402 1.3149 r
U24494/Y (XOR2X3) 0.0058 0.0531 0.0386 1.3536 f
obuf_U3105/Y (NOR2X4) 0.0056 0.0583 0.0497 1.4033 r
obuf_U3097/Y (NAND2X4) 0.0056 0.0341 0.0329 1.4362 f
obuf_U3094/Y (NOR2X4) 0.0053 0.0534 0.0421 1.4784 r
obuf_U1886/Y (AOI21X4) 0.0157 0.0607 0.0580 1.5364 f
obuf_U1861/Y (NOR3X4) 0.0101 0.1561 0.1036 1.6400 r
U24496/Y (INVX4) 0.0073 0.0442 0.0351 1.6751 f
obuf_U1760/Y (OR2X4) 0.0135 0.0378 0.0731 1.7481 f
obuf_U9462/Y (INVX12) 0.0325 0.0428 0.0358 1.7839 r
U17857/Y (OAI211X4) 0.0062 0.0992 0.0506 1.8345 f
U24495/Y (CLKINVX6) 0.0036 0.0334 0.0188 1.8533 r
we_bank_0_reg_2_/D (p_SDFFRHQX4) 0.0334 0.0000 1.8533 r
data arrival time 1.8533

clock my_clock (rise edge) 1.8000 1.8000
clock network delay (ideal) 0.0000 1.8000
we_bank_0_reg_2_/CK (p_SDFFRHQX4) 0.0000 1.8000 r
library setup time -0.0701 1.7299
data required time 1.7299
------------------------------------------------------------------------------------
data required time 1.7299
data arrival time -1.8533
------------------------------------------------------------------------------------
slack (VIOLATED) -0.1234


1. What assumptions can you make about operating conditions from this report?



2. Would this report be useful near the end (tape-out) of a chip? Please explain your answer.

3.What new parameters do you need to know to calculate the timing of the above circuit?
4.Are there new issues that are of concern with the addition of the new gate and input signal? Please describe in detail
 

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