[SOLVED] PSFB current sensing

[Porsche]

Hello everyone! I am working on PSFB based on UCC3895. **broken link removed** is practically similar to the DS’s one. Before turning it on at full power i decided to look at current waveform, so i put a load resistor at the output of the converter and have disabled feedback loop. So PWM controller provides 100% phase shift at any condition.
First, I turned on PWM controller and then I started to raise HV voltage slow. As I have some load resistor at the output, I expected to saw current waveform at Rcs also rises as I raising HV voltage. But instead, I saw that current waveform is not a right shape and it has low amplitude. What could be the reason?
My current sensor has a 1:50 transfer ratio, the secondary inductance is 3,4 mH.
Here what i got:

Spoiler: Schematic

Spoiler: PCB

1. Input current 0.522A Yellow - measured across Rcs (20R); green and red at QA and QD gates.
2. Input current 0.517A Yellow - measured across Rr (20K)

Spoiler: waveforms

1. Input current 1.016A Yellow - measured across Rcs (20R); green and red at QA and QD gates.
2. Input current 1.012A Yellow - measured across Rr (20K)

Spoiler: waveforms

Simulation shows current waveform should look more like sawtooth.

Spoiler: Simulation

P.S. I am sorry for my grammar. I hope it's not so terrible.

 

[Easy peasy]

Shoot thru can be completely avoided by choosing a suitable min dead time ....

--- Updated Jul 19, 2021 ---

p.s. also see above re R72 - delete it.

 

[Porsche]

Found mistake, CT was wired backwards, just as mtwieg said. Here are new waveforms (red is Tx voltage, yellow – voltage on C62). Now it looks more like the truth, but I still have some doubt this form is the correct one. Signal is too noisy at turn-on. Is it how it supposed to be or still something wrong with it?

Spoiler: waveforms

Removed R72 (reset resistor)

R72 = 2k

noise

Sorry to harp on, but Regarding this problem of needing the unipolar CST because it detects shoot-thru current, wouldnt you still think it better to use a bipolar CST in the bridge, and just use some sort of latching overcurrent protection for shoot thru?

I think it depends on your purposes. Maybe to generate ramp signal both these CST are suitable solutions. To actually measure current of primary the one in the bridge is obviously better solution. To measure total load current both of these solutions are bad. The only way to accurate measure load current is to measure it after LC filter at the output of the converter.

 

[cupoftea]

Signal is too noisy at turn-on. Is it how it supposed to be or still something wrong with it?

That looks like good old common mode noise coupling into your scope probe. Have you tried scoping it without a dangling ground clip? You can get those spring type probe fittings, that go over the scope ground barrel, and allow a scoping without the dreaded dangly ground thing.

 

[Easy peasy]

what is the pink signal? you dont have soft switching, insufficient dead time, caps needed across fets, more Vcc ...

 

[cupoftea]

...yes, i missed that on the pink signal, you have a Miller plateau ..so that will increase noise

 

[Easy peasy]

the pink signal is 400V high - you need more current in the fets at turn off - at the moment it just rings in the transition time due to low energy

 

[Porsche]

That looks like good old common mode noise coupling into your scope probe. Have you tried scoping it without a dangling ground clip? You can get those spring type probe fittings, that go over the scope ground barrel, and allow a scoping without the dreaded dangly ground thing.

Yes, you are totaly right. This is my ommition. I measured it again, as a normal person (using spring) and got а satisfactory result. Thank you!

Spoiler: New measurments

removed r72

replaced 20r with 40r to make amplitude slightly higher

what is the pink signal? you dont have soft switching, insufficient dead time, caps needed across fets, more Vcc ...

The pink signal is voltage across Tx primary. I have too low prmary current (<1A) to achive ZVS now, so it's predictable results. My purpose was to find why CTR didnt work, so I didn't rise primary current much. I am just missing the point about caps across fets and more Vcc. Isn't caps across fets adds more capacitance to Cds? Isn't higher Vcc increasing energy stored in Cds? Both this things should complicate ZVS at low currents but won't help to achieve ZVS earlier. Am I wrong?

the pink signal is 400V high - you need more current in the fets at turn off - at the moment it just rings in the transition time due to low energy

Could you please tell how fast should I turn off fets? 200ns will make the job done? And is the turn-on time critical in ZVS topology or it's not so important?

 

[cupoftea]

Caps across fets in PSFB is discussed by Easy Peasy here somewhat..

Phase Shift Full Bridge SMPS is massively over-hyped?

Hello, The Phase Shift Full Bridge (PSFB) converter is a hoax. –The LTspice simulation attached of a “plain” Full Bridge SMPS bears this out. PSFB claims to be able to reduce switching losses compared to the “plain” Full Bridge SMPS. However the PSFB does have Turn-OFF switching losses, just...

www.edaboard.com

Well Easy Peasy is the PSFB expert, but you dont want to turn FETs on too quickly else you may get spurious turn on of the opposite fet, and shoot thru.
Turn off, i believe fast is good especially when you have caps across the fets, as the dv/dt will not be so high with the caps across the fets.
I beleive that without caps across the fets, the turn off is a hard switched turn off in a PSFB...unlike the LLC which can give a relatively soft turn off if set up to do so .

 

[Easy peasy]

Generally speaking in a PSFB you want to turn off the fets as fast as possible for ZVS at turn off - the current commutes to the caps and then to the other device

if you have enough energy in the series inductor, caps across the fets are a good idea ( 220pF - 1nF ) as they reduce RFI as well as turn off losses - this is standard on our 6kW psu's

p.s. our gate drive can pull the Vgs down in about 30nS from 15 - 0 V.

If you have enough energy for a nice resonant ring to the other rail - turn on speed is not so important - just so long as the fet is fully on in a reasonable time.

--- Updated Jul 21, 2021 ---

p.s. the new CT waveform looks a lot better ...

 

[Easy peasy]

Just looking at the CT reading - you barely have 1A peak in the fets ...

 

[mtwieg]

At a glance, waveforms look typical for very light load operation. Next step is to increase current, reduce phase shift, and check ZVS conditions and efficiency.

 

[Porsche]

Thank you so much for your helping, guys! I could make my converter stabilaze primary current now (by adjusting voltage at R21). Next thing I will increase bus voltage and will try to stabilize output voltage by connecting feedback loop back and will check ZVS condition.
I wonder what is the common method to check ZVS? I can measure Vds and Vgs and if they don't overlap so ZVS is achieved or it have something to do with Miller plateau? Like if there is no Miller plateau at Vgs so transistor has ZVS? For example I took waveforms again:

Spoiler: waveform

Green and Pink is Vgs at QA and QD. I clearly see no Miller plateau at green waveform. Does this mean ZVS achieved in this leg? And no ZVS achived in the pink one as it some sort of oscillations in plateau region?

 

[cupoftea]

If you have a miller plateau at turn on, it means that the voltage Vds across the fet was not zero (or near zero) when the fet started to turn on........so yes it means its not soft switching.
The miller plateau at turn on, kind of represents the fall of the vds (Vgd) voltage from a high value down to the vds on voltage, which is near zero.....so in other words.....it means that when your fet started to turn on...the vds must have been high....so yes , miller plateau = no soft switching


The zvs method involves having a circulating current which is lagging the switching voltage..so when the top fet turns off, the laggardly circulating current starts discharging the bottom fet's cds, and when it has done so, you then turn on the bottom fet with now a nice zero voltage across its vds.

If you want, Read page 6 of this to see what happens when a fet turns on in a hard switched way, and the miller plateau shows its ugly head

http://www.radio-sensors.se/download/gate-driver2.pdf