PSFB abnormal heating and current oscillations

[Albert.b]

Hello everyone,


I am designing a PSFB converter with a current doubler topology in the rectification stage, using the UCC28951PWR controller. The rest of the circuit follows the topology provided in the datasheet: the drivers and the controller are referenced to the secondary ground, and the full-bridge MOSFETs are driven through gate drive transformers. The input voltage range is 30–120 V, the output voltage is 14 V, and the total output power is 1 kW.

The issue I am facing is that the full-bridge MOSFETs are heating up excessively—reaching 90°C in just one minute of operation at a 3 A load.

(Lagging leg - Left-side / Leading leg - Right-side)

As far as I can tell, ZVS is being achieved in both legs for all the possible loads, which to he honest, it's a bit odd to me as ZVS is meant to happen at higher loads, so I may be missing something here.

I am attaching an image that shows the switching behavior on the lagging leg for a load of 3A, and amall shim inductor (0.22uH) in series with samll tx leackage inductance (0.044uH) :

• Yellow: Voltage at the intermediate node of the branch.
• Green: High-side MOSFET gate voltage.
• Blue: Low-side MOSFET gate voltage.

Until now, I have only been monitoring the MOSFET gate voltages, which do not reveal everything. If abnormal current is flowing through the body diode, it may be hidden from my observations. To gain better insight, I placed a shunt resistor in series with the high-side MOSFET of the leading leg to monitor the current flow for any irregularities.

The first set of measurements (see attached image) shows the following waveforms for the leading leg:

• Yellow: Current through the high-side MOSFET.
• Green: High-side MOSFET gate voltage.
• Orange: Voltage at the intermediate node of the branch.
• Blue: Low-side MOSFET gate voltage.

The concern arises when a large current oscillation appears in the MOSFET while its channel is disabled, which I suspect is causing the heating issue.

In another measurement, the waveforms observed are:

• Yellow: Voltage at the middle node of the leading leg.
• Green: Current through the low-side mosfet of the leading leg(A).
• Orange: Voltage at the middle node of the lagging leg.

Another observation is that the current oscillations through the MOSFET occur when any MOSFET in the bridge turns off and the node at the midpoint changes its voltage value. In a PSFB converter, when a MOSFET turns off, the voltage at the midpoint shifts polarity (from 0 to Vin or vice versa) because the parasitic capacitances in the branch of the MOSFET are charged and discharged by the current maintained briefly by the transformer’s inductance. This rapid voltage change might be causing the oscillations, as the inductance in the current path resonates with other elements.

If that’s the case, I’m unsure what changes I could make to the schematic to suppress these oscillations.

When comparing the experimental waveforms with a simulation of the same circuit under identical conditions, it was observed that, aside from the noise present in the real implementation, the current waveforms through the MOSFETs match closely:

The theoretical circuit does not exhibit ringing, but it does appear in the physical implementation. Therefore, the issue could stem from the PCB design or the way the components are arranged. Additionally, the current paths in each switching cycle can be described as follows:

• The current path during one half-cycle, which forms an almost closed loop (Red).
• The current path during the other half-cycle, which extends further, forming approximately one and a half loops (Blue).

But this is just an observation as I am not sure.
Iam attaching the schematics and the images in case the quality is too low.

Any help would be very much appreciated, thank you

 

[kd502]

Did you use scope probe ground clip? Ringing everywhere look like scope probe grounding problem.
Ground connection must be as short as possible:

Gate voltage rise and fall times look quite long. Zoom in the slope of the gate voltage and drain voltage try to estimate the switching times, calculate the switching losses.

 

[Albert.b]

Hello,


This "noise" or ringing appears regardless of which probe I use — even with the current probe. I believe it's real and likely the cause of my heating issue.


Regarding the rise and fall times, perhaps you were referring to the second image, where they do look a bit slow. I’ve tested many gate resistor values, even removing them entirely, until the transitions were fast enough. Yet, the heating problem persisted. Also, if I'm achieving ZVS, then the rise time shouldn’t matter that much, right?


Here are some of the questions I have related to this heating issue:

• Am I using the correct topology? I've been using a current doubler rectification topology because I assumed it was compatible with the UCC28951PWR controller, even though this topology is not shown in the datasheet.
• Am I truly achieving ZVS (as it seems in the second image), or am I missing something? To me, it doesn't seem normal to achieve ZVS with loads as light as 3A. So maybe I’m misinterpreting the oscilloscope waveforms.

This problem feels quite fundamental — more like a conceptual error rather than just a matter of component selection.

 

[kd502]

This "noise" or ringing appears regardless of which probe I use — even with the current probe.

Current waveforms usually have more ringing. When I see ringing on gate signal I suspect probe ground I'm not talking about which probe you used but how you connected ground of that probe.
Did you use spring shown in my picture ?

I believe it's real and likely the cause of my heating issue.

Ringing usually have small energy. Exception is when high and low side switch conducts. In that case ringing is not the cause.
Show us the waveform with current falling slope stretched to whole screen.

Am I truly achieving ZVS (as it seems in the second image), or am I missing something? To me, it doesn't seem normal to achieve ZVS with loads as light as 3A. So maybe I’m misinterpreting the oscilloscope waveforms.

Looks like ZVS. Current flows through the inductive load. Nothing unexpected.

This problem feels quite fundamental

Fundamental question. What are the switching loses? Transistors without heatsink can dissipate only 1W. Do the math. Is it possible or not?

Also, if I'm achieving ZVS, then the rise time shouldn’t matter that much, right?

Rise time doesn't matter but fall time matter. You have hard switching there.
What is the peak current before turn-off?

 

[mtwieg]

My first guess would also be that most of the observed ringing is not "real" and is the result of how the signals are probed... but the fact that you're observing such heating indicates a real issue.

This "noise" or ringing appears regardless of which probe I use — even with the current probe.

Please describe what probes you're using in detail.
For example, you show waveforms of high side Vgs, is this measured with a differential probe or by subtracting two measurements?
Also you mentioned above measuring current by measuring voltage across a shunt resistor, but here you mention a "current probe". The distinction between the two is very important. Also need to know which side of the FET the current is measured on.
These details affect whether we assume the ringing is "real" or not.

In practice, ringing like this usually originates from the rectifiers on the secondary side. Are you using any snubbers on the secondary? Are you using synchronous rectifiers?

 

[Easy peasy]

lack of quality film caps ( or MLCC suitably rated ) across the fets on the H bridge - top D to bottom S

this is a classic newbie thing

 

[Easy peasy]

@Albert.b just to recap - the reason for the overheating mosfets is the lack of heat-sinking.

not helped by how far apart the fets are - with no local decoupling - causing HF ringing

 

[Albert.b]

Current waveforms usually have more ringing. When I see ringing on gate signal I suspect probe ground I'm not talking about which probe you used but how you connected ground of that probe.
Did you use spring shown in my picture ?

I hadn’t tried using the clip technique you suggested until now. In some cases, I managed to get cleaner signals. For instance, when measuring the gate signal, I did notice a clear improvement compared to the regular long ground lead.

However, when I probed the Vds of the MOSFETs, the noise remained visible — in fact, it sometimes looked slightly worse with the clip.

What I can say for sure is that the noise strongly depends on how the probe is connected, which suggests that it might not be real, or at least not the root cause of the heating issue. It seems to be coming from somewhere else.

Ringing usually have small energy. Exception is when high and low side switch conducts. In that case ringing is not the cause.
Show us the waveform with current falling slope stretched to whole screen.

Fundamental question. What are the switching loses? Transistors without heatsink can dissipate only 1W. Do the math. Is it possible or not?

I’ve done a more detailed analysis of the switching losses at turn-off, specifically on the low-side FET of the leading leg. It might actually be the root of the problem.

In my simulation, I noticed a significant overlap of voltage and current during turn-off:
Channels shown:
Red → Power dissipated by the MOSFET
Green → Current flowing through the MOSFET
Yellow → V_DS voltage
Blue → Gate voltage V_GS

To mitigate this hard-switching effect, I added a 20 nF capacitor across the MOSFET, as suggested in this TI post, which describes a situation very similar to mine:

"I think the key to zero-voltage turn-off is shaping the voltage rise across the switching FET by tuning the LC of the system. Because my primary is low voltage high current, my somewhat uncontrolled leakage and path inductances where causing the voltage rise at turn-off to set off like a bullet from a gun. I rewound my transformer to absolutely minimise leakage by interleaving and being incredibly neat - which involved bringing the transformer wires out as flying leads which I took as directly to the semiconductors as I could. The second part of the shaping was to add 22n across the drain-source of all four FETs."

In the simulation, this modification eliminated the power spike:

In my real circuit, adding the 20 nF capacitor in parallel with the MOSFETs reduced the turn-off switching losses, and gretly reduced the noise present on the current waveform (green). However, the heating issue still persists.

So I calculated the actual switching losses from the osciloscope waveforms. From the Vds and Id waveforms during turn-off, I plotted the power curve and integrated the area to obtain the energy loss, and then multiply for the frequency to obtain dissipated power. The result was surprisingly low: about 0.1 W.

That said, if we take into account the negative current tail that remains (even with the snubber cap), we might be dealing with significant reverse recovery losses.

I ran the numbers, and the estimated reverse recovery losses are around 3.1 W, which could very well explain the overheating.
If this is the case, I'm not sure how I could tackle this issue and solve the reverse recovery problem.

Rise time doesn't matter but fall time matter. You have hard switching there.
What is the peak current before turn-off?

Now it can be seen on the last two screenshots from osciloscope. The peak current at the switch off time is 20A.

Thank you very much for your comments — they’ve been incredibly helpful. I really appreciate the time and knowledge you're sharing.

 

[Albert.b]

My first guess would also be that most of the observed ringing is not "real" and is the result of how the signals are probed... but the fact that you're observing such heating indicates a real issue.

You might be right. Based on what I explained in my previous reply, I'm increasingly suspecting that the noise is just coupled interference on my probes, and that I shouldn't focus on it anymore, as I no longer believe it's the actual source of the problem, but more likely a consequence or not even real at all.

Please describe what probes you're using in detail.

For example, you show waveforms of high side Vgs, is this measured with a differential probe or by subtracting two measurements?
Also you mentioned above measuring current by measuring voltage across a shunt resistor, but here you mention a "current probe". The distinction between the two is very important. Also need to know which side of the FET the current is measured on.
These details affect whether we assume the ringing is "real" or not.

For the green and yellow signals, I'm using isolated differential probes. In the case of the green signal, I'm measuring the voltage drop across a 0.01-ohm shunt resistor, which is soldered in series with the source of the low-side MOSFET in the leading leg.
That's why there's so much noise on that signal — I'm measuring a very small voltage drop directly and multiplying it by 100 to get the current displayed directly in amps.
The probes I'm using are the following:

The rest of the probes I'm using are Tektronix differential probes:

I later replaced the ground clip of these probes with the spring ground tip you suggested, which in some cases helped reduce noise in the signal — especially when measuring the MOSFET gate voltage.

When I say I measure V_GS, I’m referring to the differential voltage between the gate and source—without subtracting two signals.

Regarding the current issue, I’m also using a current probe to measure the primary-side current, which can also pick up noise. However, in the case of the green curves I showed earlier, I’m referring to the current I observe using the improvised shunt resistor.

In practice, ringing like this usually originates from the rectifiers on the secondary side. Are you using any snubbers on the secondary? Are you using synchronous rectifiers?

I am using an RDC snubber on the seccondary side as well as clamping Schottky diodes on the primary.

 

[Albert.b]

@Albert.b just to recap - the reason for the overheating mosfets is the lack of heat-sinking.

not helped by how far apart the fets are - with no local decoupling - causing HF ringing

Thanks for your feedback. I followed your suggestion and added parallel capacitors, which reduced current waveform noise and switching losses—but the overheating remains. Do you have any further suggestions based on these latest changes?

 

[Easy peasy]

@Albert.b as said above - you simply don't have enough heatsinking for the losses in the fets - if you know the rms current in a device and its R-ds-on at temperature you can work out the ( best case ) conduction losses - you can then apply this as DC in your fets on a blank pcb and look at the temp rise - if it is too much - your board needs to change.

--- Updated Apr 23, 2025 ---

In my real circuit, adding the 20 nF capacitor in parallel with the MOSFETs reduced the turn-off switching losses

OK - I don't advise putting more than 2n2 across any single mosfet - assuming you have ZVS operation with some head-room

My text was to suggest putting film caps from the top fets drains ( HVDC + ) to the bottom fets sources ( 0v - HVDC ) - to soak up the currents at turn off - not too much as it will affect what you see in your CT - say 100 - 330nF max, a rail damping snubber may be useful too, say 100nF in series with 4E7 ( needs experimenting )

this is often overlooked.

As to temp rise - see above

--- Updated Apr 23, 2025 ---

footnote:

" I ran the numbers, and the estimated reverse recovery losses are around 3.1 W, which could very well explain the overheating.
If this is the case, I'm not sure how I could tackle this issue and solve the reverse recovery problem ".

ah - no - your so called "recovery current" is all in the parallel capacitors = no losses in the fets ( or a lot less than 3.1W )

--- Updated Apr 23, 2025 ---

Lastly - your fet turn on is too aggressive - rather than 0.0 ohms - try 15 ohms turn on resistance R3,4 R25,26

make sure the max dead time is not too long, e.g. 600nS would be too long - a long dead time means the internal diode is carrying the ZVS current before the fet turns on and the current reverses for a power pulse to the Tx, internal diode is ~ 0.8V x 20A = 1.6 watts for the period this is the case, for say 300nS in 5.2uS this is another 100mW in the fet. You get the idea.

--- Updated Apr 23, 2025 ---

Can we please see turn on waveforms as well ? totem poles and assoc gate drive

--- Updated Apr 23, 2025 ---

OK - more obvious engineering errors: stated power = 1kW ( desired ) stated min Vin = 30V, this is 33.33 amps ave from the supply

the stated fets are 9.5m-Ohm @ 75 deg C ( data sheet ), assuming they carry 35A rms half the time, at 30VDC input - they will each dissipate, 35^2 x 0.0095 ohm / 2

= 5.8 watts each ( conduction only ) - this is way too much for the heat-sinking you have shown in the images

what you have shown is good for 1.5 watt per fet, maybe, for 9.5m-Ohm this is 12.5 amps rms, or 17.78 amps when ON.

What ave input current do you have on your converter when the fets get to 80 deg C in a stable fashion ?

--- Updated Apr 23, 2025 ---

Notice this gate rise of the green gate voltage:

this may cause shoot thru and extra losses in this mosfet pair - although here - as it is after the turn off of the other device - the effect is less severe . . . still - better if the gate drive held the high side G-S low as the voltage changes on the midpoint.

 

[Albert.b]

" I ran the numbers, and the estimated reverse recovery losses are around 3.1 W, which could very well explain the overheating.
If this is the case, I'm not sure how I could tackle this issue and solve the reverse recovery problem ".

ah - no - your so called "recovery current" is all in the parallel capacitors = no losses in the fets ( or a lot less than 3.1W )

However, I'm observing this "reverse recovery" current through a shunt on the drain of the low-side MOSFET while its channel is disabled, so I believe it is actually flowing through the MOSFET. Am I misunderstanding something?

Lastly - your fet turn on is too aggressive - rather than 0.0 ohms - try 15 ohms turn on resistance R3,4 R25,26

Sorry, I currently have a 3.1 Ω resistor on each gate, plus another 3.1 Ω at the driver output, which differs from what’s specified in the datasheet.

Can we please see turn on waveforms as well ? totem poles and assoc gate drive

MOSFET turn-on waveforms, using the same color code as in the previous captures:

• Green: driver signal
• Yellow: gate of the high-side MOSFET (lagging leg)
• Orange: gate of the low-side MOSFET (lagging leg)

OK - more obvious engineering errors: stated power = 1kW ( desired ) stated min Vin = 30V, this is 33.33 amps ave from the supply

the stated fets are 9.5m-Ohm @ 75 deg C ( data sheet ), assuming they carry 35A rms half the time, at 30VDC input - they will each dissipate, 35^2 x 0.0095 ohm / 2

= 5.8 watts each ( conduction only ) - this is way too much for the heat-sinking you have shown in the images

what you have shown is good for 1.5 watt per fet, maybe, for 9.5m-Ohm this is 12.5 amps rms, or 17.78 amps when ON.

At the moment, I have two MOSFETs in parallel with a fairly large heatsink. Since the input can go up to 120 V, these are the best MOSFETs I could find for the job. For now, they’re soldered upside down and exposed, to make thermal behavior easier to observe and signal probing more convenient. I didn’t expect them to heat up under light loads, which is why they’re temporarily mounted like this. The final setup will have them mounted on the bottom side of the PCB, bent 90 degrees and thermally coupled to a thick aluminum heatsink. If the issue turns out to be a roughly constant 4 W of dissipation, that should be resolved with proper heatsinking. But to be honest, I didn’t expect any noticeable heating under such a low load while they're in free air.

What ave input current do you have on your converter when the fets get to 80 deg C in a stable fashion ?

Interestingly, with just 3 A at the output, I already observed heating up to 90 °C, although the temperature was rising relatively slowly.

--- Updated Apr 23, 2025 ---

Notice this gate rise of the green gate voltage:
View attachment 199181
this may cause shoot thru and extra losses in this mosfet pair - although here - as it is after the turn off of the other device - the effect is less severe . . . still - better if the gate drive held the high side G-S low as the voltage changes on the midpoint.

This was the noise that initially concerned me. However, I’m not entirely sure how much of it is actually probe-coupled noise.

Thanks for your comments. I tried adding the multilayer capacitors as you suggested, but the issue is still present.

 

[mtwieg]

In my simulation, I noticed a significant overlap of voltage and current during turn-off:
Channels shown:
Red → Power dissipated by the MOSFET
Green → Current flowing through the MOSFET
Yellow → V_DS voltage
Blue → Gate voltage V_GS
View attachment 199164
To mitigate this hard-switching effect, I added a 20 nF capacitor across the MOSFET, as suggested in this TI post, which describes a situation very similar to mine:

In the simulation, this modification eliminated the power spike:
View attachment 199166

These simulated waveforms don't make sense to me. Vgs shows a prominent miller plateau, but Vds and Ids do not start changing until long after the plateau occurs. Something isn't right...

Also it's not clear what you mean by the "leading" and "lagging" legs, typically I see the legs referred to as "active" and "passive".

As for those spikes in your measured current, I don't see why you think they're due to reverse recovery (reverse recovery of what? If it was due to RR in that FET's body diode, then one would expect the spikes to have opposite polarity).

Those spikes might just be due to ESL in your current shunt resistor. This will cause a highpass filter effect.

But the current waveforms are so nasty it's hard to know to what extent they are believable representations of the actual drain current.

 

[Easy peasy]

The last set of pictures - of the gate waveforms seems very clean - which is nice, the dead time may be just a little long, though,

there is one little known phenomena of the ph shift full bridge that can affect certain mosfets in certain circuits:

and that is - if there is insufficient reverse current in the mosfet before it is turned on ( and then the current reverses to normal direction ) then some weird effects can be triggered in the parasitic BJT inside the device - this classically occurs at low load - as you are seeing - and has been responsible for a lot of field failures in power supplies from some big name manufacturers. Some of the noise present in the waveforms strongly suggests this might be the root cause.

The only cures here are better ( different ) mosfets, or more circulating current at light loads, here you could try one fet in each position - rather than 2 in parallel,

and just on this note - some mosfets DO NOT like being in hard parallel ( usually those with low internal gate R ) - we have seen blow ups from this sole cause - so worth trying just the one fet in each spot,
for paralleling - you need AT LEAST a small ferrite bead in each gate, or say 3.3 -> 10 ohm in EACH gate ( with a reverse diode for fast turn off )

You can also try SiC mosfets, and see if the low load temp rise still occurs - these are much more resistant to adverse behaviour at light load ZVS - the paralleling guidelines still apply however.

good luck !

--- Updated Apr 24, 2025 ---

p.s. - we still can't see the size of the actual heat-sinks, they look small on the thermal picture, do you know the Rth: sink->air of those you have used ?
for example if they are 20 deg C per watt under the most favourable circumstances, this is a Trise of 80 deg C for 4 watts.
So in a 20 deg C ambient - they would tend to 100 deg C, of course the Rds-on will be higher with temp - leading to extra losses and a spiraling temp rise . . . .

 

[Easy peasy]

However, I'm observing this "reverse recovery" current through a shunt on the drain of the low-side MOSFET while its channel is disabled, so I believe it is actually flowing through the MOSFET. Am I misunderstanding something?

OK - fets have capacitance - and this can be high-ish at low D-S volts - you need experience to discern what is capacitive current flow in a mosfet ( lossless ) - and what is other current flow - e.g. backwards diode current.

Sometimes - if the drain voltage on a lower fet flies up really fast ( aggressive turn on of the upper fet ) - this is coupled via the D-G capacitance of the lower fet to the gate, and can pull up the gate voltage inside the mosfet ( and you can often see an effect on the gate terminal ) and cause a short conduction pulse through the lower fet - this is sometimes called a minor shoot thru by experienced engineers - this causes heat and RFI ( noise ) and can lead to random failures in the field especially at higher temps where the gate threshold voltage is lower (!)

This also happens for a top fet when the bottom fet is slammed on hard and fast causing high dv/dt on the top fet.

So - you see - there is lots to consider and know about when designing high power converters with mosfets - if you have not done similar before @Albert.b

--- Updated Apr 25, 2025 ---

p.s. your dead time of apparently 700nS appears to be too large.

 

[24vtingle]

You can also try SiC mosfets, and see if the low load temp rise still occurs - these are much more resistant to adverse behaviour at light load ZVS

So would you advise OP to also provide a +/- gate drive for the SiC FETs aswell?
I recently got quite a "good hiding" during an interview by the top engineer from a very well known defence contractor for saying that +/- gate drive was not absolutely necessary for SiC drive. They were doing a mains inverter and were using SiC FETs.

 

[Easy peasy]

Depending on power levels -5V is recommended for SiC by the big players, as there is the issue of Vgs-thres shift ( downwards ) over time, also it is generally a lot easier to provide -5V than a really solid 10m-Ohm G-S at all frequencies for OFF drive.

High dv/dt circuits benefit from -10V

 

[24vtingle]

Depending on power levels -5V is recommended for SiC by the big players, as there is the issue of Vgs shift ( downwards ) over time,

Thanks, i agree they seem to want that, but its hard to believe SiC VGSth will get lower than VGSth for a typical Si FET over time?

If the -5V Vgs is needed for SiC then it would surely also be needed for Si FETs? Its not as if Qgd/Qgs is any more for a SiC FET
FET than for a Si FET.

A -5V drive on Vgs sounds better indeed...but better for both Si and SiC.

 

[Easy peasy]

try reading some data sheets, lots of SiC devices have low Vgate-thres at higher temps . . .

As to ratios of capacitance and charge - again different makers have differing results here, and dv/dt per circuit comes into it.

 

[24vtingle]

Thanks, with digikey being down (for a long time now?) its not so easy to find and compare stuff now.

https://www.mouser.co.uk/datasheet/2/848/WNSC2M150120W-3436614.pdf

In the above SiC FET, the VGSth does indeed go down to 1.9V at 175degsC...but a look at fig 9 shows that the transconductance is low at this value of VGS....and in fact, even at 175degC, the VGS has to be above about 3.5V before any even small IDS current flows....and really, even at 175degC, even with VGS = 6V, only 4A of IDS will flow....hardly a disastrous shoot-through.
So the question remains (to the SiC fraternity in general) as to why a neg VGS drive is needed for SiC and not for Si, and this is given in the below linked article from Microsemi
I believe this is beneficial to OP?

Here's a 650V Si FET in comparison...

https://www.onsemi.com/download/data-sheet/pdf/fcpf099n65s3-d.pdf

..At least from these 2 datasheets of Si and SiC, its difficult to see why SiC needs a neg VGS drive and Si doesnt? Surely they would both benefit from it the same? Neither needs it more than the other.

If anything, from those 2 datasheets, the real reason an SiC FET benefits more from neg drive is that its body diode has bigger Vf with neg VGS...and thus current could be diverted more readily into an anti-parallel SiC diode and so bring about no (or less) reverse recovery. A normal Si FET has no increase of its internal diode's Vf with increasing neg VGS drive. However, read the following and indeed you wouldnt want to use SiC without neg VGS drive...

https://ww1.microchip.com/downloads/aemDocuments/documents/PSDS/ApplicationNotes/ApplicationNotes/Microsemi_SiC_MOSFETS_Design_Recommendations_Application_Note.pdf