Pseudo Random Binary Noise Generator

[steven_arnold_85]

pseudo random vhdl

Hello,

I asked a similar question earlier to this one except that I wanted to implement a pseudo random binary noise generator using physical hardware. That worked well.

Now I am wondering how I would go about implementing one on an EPLD. Does anyone know of where I might go about finding some code written in a form that can be implented on an ALTERA chip? I was hoping to write in VHDL. I am familiar with it so I was hoping someone could give me some code in that form.

Thankyou


Oh, for those of you that don't know, pseudo random is different to truely random in that if the generator is restarted, the exact same pattern of numbers will be "spat" out again. Truely random generators would produce a new set of numbers.

 

[vishwa]

noise generator verilog

Hi

Do you want to generate a signal with random bit stream? or pseudo random code for spread spectrum communication.?

let me know clearly. If you want the first one, I can give you a simple VHDL code to generate random binary signal


Regards,
Vishwa

 

[echo47]

pseudorandom vhdl

One very easy method is to use an LFSR. That's a shift register with an XNOR feedback gate and a one-bit output. Here is an 18-bit LFSR in Verilog (probably easy translate to VHDL):

module top (clk, noisebit);
  input             clk;
  reg        [17:0] lfsr=0;
  output            noisebit;

  assign noisebit = lfsr[0];

  always @ (posedge clk)
    lfsr <= {lfsr, lfsr[17] ~^ lfsr[10]};
endmodule

Nice Xilinx app notes with table of different length registers:
https://www.xilinx.com/bvdocs/appnotes/xapp210.pdf (best)
https://www.xilinx.com/bvdocs/appnotes/xapp052.pdf

 

[steven_arnold_85]

binary noise

Hello,

I want to generate a signal with random bit stream. Would you be able to show me the VHDL code for this please?

Thankyou

 

[echo47]

random bit generator + vhdl

My small Verilog module does that. I'll run it through a VHDL converter ...

ENTITY top IS
  PORT (
    clk           : IN bit;
    noisebit      : OUT bit);
END top;

ARCHITECTURE translated OF top IS
  SIGNAL lfsr     :  bit_vector(17 DOWNTO 0) := "000000000000000000";

BEGIN
  noisebit <= lfsr(0) ;

  PROCESS
  BEGIN
    WAIT UNTIL (clk'EVENT AND clk = '1');
    lfsr <= lfsr(16 DOWNTO 0) & (lfsr(17) XNOR lfsr(10));
  END PROCESS;

END translated;