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-- Company:
-- Engineer:
--
-- Create Date: 13:11:30 05/17/2010
-- Design Name:
-- Module Name: charshift - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity charshift is
Port ( clk : in STD_LOGIC;
inputchar : in STD_LOGIC_VECTOR (6 downto 0);
char1 : out STD_LOGIC_VECTOR (6 downto 0);
char2 : out STD_LOGIC_VECTOR (6 downto 0);
char3 : out STD_LOGIC_VECTOR (6 downto 0);
char4 : out STD_LOGIC_VECTOR (6 downto 0) );
end charshift;
architecture Behavioral of charshift is
signal char1sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char2sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char3sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char4sig : STD_LOGIC_VECTOR (6 downto 0 );
begin
char1 <= char1sig;
char2 <= char2sig;
char3 <= char3sig;
char4 <= char4sig;
process(clk)
begin
if ( clk = '1' and clk'event) then
if (inputchar /= char1sig) and (inputchar /= "1111111") then
char1sig <= inputchar;
char2sig <= char1sig;
char3sig <= char2sig;
char4sig <= char3sig;
else if (inputchar = char1sig) and (inputchar /= "1111111") then
--??
--??
--??
end if;
end if;
end process;
end Behavioral;
if [COLOR="red"](inputchar /= char1sig) and[/COLOR] (inputchar /= "1111111") then
char1sig <= inputchar;
char2sig <= char1sig;
char3sig <= char2sig;
char4sig <= char3sig;
[COLOR="red"]else if (inputchar = char1sig) and (inputchar /= "1111111") then
--??
--??
--??[/COLOR]
end if;
I've made a counter with a frequency of 5 Hz and the code is working. But when I don't press any button, the screen is filling itself with the previous pressed numbers but I want the screen to stop shifting the digits when no button is pressed. Thanks for the help.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity charshift is
Port ( clk : in STD_LOGIC;
inputchar : in STD_LOGIC_VECTOR (6 downto 0);
char1 : out STD_LOGIC_VECTOR (6 downto 0);
char2 : out STD_LOGIC_VECTOR (6 downto 0);
char3 : out STD_LOGIC_VECTOR (6 downto 0);
char4 : out STD_LOGIC_VECTOR (6 downto 0) );
end charshift;
architecture Behavioral of charshift is
signal char1sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char2sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char3sig : STD_LOGIC_VECTOR (6 downto 0 );
signal char4sig : STD_LOGIC_VECTOR (6 downto 0 );
begin
char1 <= char1sig;
char2 <= char2sig;
char3 <= char3sig;
char4 <= char4sig;
process(clk)
begin
if ( clk = '1' and clk'event) then
if (inputchar /= "1111111") then
char1sig <= inputchar;
char2sig <= char1sig;
char3sig <= char2sig;
char4sig <= char3sig;
end if;
end if;
end process;
end Behavioral;
to Nexys2
and your counter
Can you post your code?
Alex
How can it "walk" now when it didn't before, if "1111111" is the signal when no key is pressed then it shouldn't happen.
I also don't see a delay (as a counter at least), where did you change your clock frequency to /10000000
Alex
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PS2tochar is
Port ( sc : in STD_LOGIC_VECTOR (7 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0) );
end PS2tochar;
architecture Behavioral of PS2tochar is
Signal char : STD_LOGIC_VECTOR (7 downto 0);
begin
process(sc)
begin
case sc is
WHEN "01000101" => sevenseg <= "1000000"; -- 0
WHEN "00010110" => sevenseg <= "1111001"; -- 1
WHEN "00011110" => sevenseg <= "0100100"; -- 2
WHEN "00100110" => sevenseg <= "0110000"; -- 3
WHEN "00100101" => sevenseg <= "0011001"; -- 4
WHEN "00101110" => sevenseg <= "0010010"; -- 5
WHEN "00110110" => sevenseg <= "0000010"; -- 6
WHEN "00111101" => sevenseg <= "1111000"; -- 7
WHEN "00111110" => sevenseg <= "0000000"; -- 8
WHEN "01000110" => sevenseg <= "0010000"; -- 9
WHEN OTHERS => sevenseg <= "1111111";
end case;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clkdivider2 is
Port ( A : in STD_LOGIC;
B : out STD_LOGIC);
end clkdivider2;
architecture Behavioral of clkdivider2 is
signal D : STD_LOGIC;
signal count: integer;
signal divide: integer := 1000000;
begin
Process (A)
begin
B <= D;
if falling_edge(A) then
count <= count + 1;
if count = divide then
D <= not D;
count <= 0;
end if;
end if;
end process;
end Behavioral;
if (inputchar /= "1111111") then
char1sig <= inputchar;
char2sig <= char1sig;
char3sig <= char2sig;
char4sig <= char3sig;
If you clock is 50MHz and you invert D every 1000000 clocks then D has a frequency of (50M/1M)/2 =25Hz,
you have a half period every 1000000 times.
I can't understand what is going wrong but this code wouldn't "walk" if inputchar was "1111111"
Code:if (inputchar /= "1111111") then char1sig <= inputchar; char2sig <= char1sig; char3sig <= char2sig; char4sig <= char3sig;
if you add (inputchar /= char1sig) then you will not be able to detect the same character again.
Alex
Probably, you want to detect release codes as well as press codes?
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