Proximity effect and threshold voltage

[VLSI_Learner]

I was reading an article regarding Layout dependent proximity effect.
In the section under "Why should I care about this effect?", I got this -

1. Proximity effects can de-rate FET current by 10% (or more), or shift
threshold by several 10’s of mV.
2. • De-rating factors can only be calculated after layout extraction,
i.e., ignored in schematic-extracted netlists.


Can you please explain both the points. I couldn't get the meaning of it.

Thank a lot in advance

 

[erikl]

1. Because of higher nwell doping near the nwell edges, s. the presentation I've linked to in this thread.

2. WPE is a process-conditioned effect and depends on the position of a MOSFET in relation (distance) to the well edge. Schematic symbols have no info about such position.