Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
What do you mean by bitwise sum? Do u want top mean the LSB of the' resut of summatio'n? The reason I ask this because the binary sum will have sum and carry and the sum can be a binary value whose decimal equivalence is more than 1.
I think the meaning of "bitwise sum" is obvious from the code. The only point, that may need explanation is the used bitwidth in calculating assign sum = in[0] + in[1] ...
It can be derived from Verilog Rules for expression bit lengths. This is a case of context-determined expression, where the maximum bitlength of left hand and right hand side of the expression is used. Thus all possible carries are considered correctly.
if a number is power of 2, only one bit will be equal to one, other one bit to zero. quite easy check, as describe by dcreddy1980, with the sum all individual bit.
Even a binary number having odd no. of 1s will produce the sum to be one, but still it is not power of 2. Is not it?
fvm
But how will you store the carry and full sum? Even a binary number having odd no. of 1s will produce the sum to be one, but still it is not power of 2. Is not it?
You didn't pay attention to the definition [2:0] sum. The sum for odd numbers can be also 3 in the present example. For the detail behaviour of the add operation, see my previous post.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.