prototype ASIC design into altera FPGA

[willzz]

Hi all,

I am trying to prototype a design into FPGA(Altera). Right now I am having difficulties closing setup timing. critical timing path seem to have very long net routing delay.

The way to fix in ASIC is to break the long net into sections and insert buffers if needed, or simply upsize the driver strength.

I am using the quartus prime v16 lite version for the implemention. and I dont have a lot of FPGA experience.

Can someone please give me some ideas? to implement something similar to what i mentioned above? or provide alternative solutions ?

Thanks!!

 

[dpaul]

Right now I am having difficulties closing setup timing. critical timing path seem to have very long net routing delay.

Are the nets in question reset and/or clock nets?

For clock nets simply use clock buffers. In Xilinx FPGA the buffers are called BUFG.

For resets, use localized resets. There is a nice white paper on this:
https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

[willzz]

Hi,

no, those nets are not clock nets or reset nets. they are the nets in the datapath(mostly between computational logics)

and the FPGA i am using is Cyclone V... it is a pretty slow speed grade fpga. and I am running 300 MHz on it( not too fast i guess )

 

[ThisIsNotSam]

300Mhz is pretty fast depending on your design.

 

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Cyclone parts including V aren'tmeant for ASIC prototyping the express purpose of those parts is low cost, I.e. not cutting edge performance. Use either a Stratix or Xilinx Virtex or Ultrascale part.