Start with how and where, referred to what, the "high voltage"
will be imposed. Some classes of fault become unlikely when
things are assembled (like, the driver may be what protects
the gate from gate-node "stimulus" by its own ESD network).
You can't prevent every scenario but some prevent themselves
in the end.
Avalanche rated FETs will take some abuse on the drain (as long
as the source is tied down well w.r.t. the threat source - the
return path matters as much as the "injection point").
There exist some FETs with built in gate protection zeners.