Process(CLK50) is
If(rising_edge(CLK50))then
CLK25<=NOT(CLK25)
End if;
End Process;
Process(CLK25) is
If(rising_edge(CLK25))then
CLK10<=NOT(CLK10)
End if;
End Process;
Clock25: process(CLK_50)
begin
if(rising_edge(CLK_50))then
if(en_Clk25='1')then
CLK_25<=NOT(CLK_25);
end if;
end if;
end process;
Clock10: process(CLK_50)
begin
if(rising_edge(CLK_50))then
if(en_Clk10='1')then
if(count10<half10)then
CLK_10<='1';
count<=count+'1';
else
CLK_10<='1';
count<=count+'1';
if(count=max10)then
count<=(others => '0');
end if;
end if;
end if;
end if;
end process;
Clock5: process(CLK_50)
begin
if(rising_edge(CLK_50))then
if(en_Clk5='1')then
if(count5<half5)then
CLK_5<='1';
count<=count+'1';
else
CLK_5<='1';
count<=count+'1';
if(count=max5)then
count<=(others => '0');
end if;
end if;
end if;
end if;
end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 signal cnt : unsigned(3 downto 0) := (others => '0'); signal en_1_in_16 : std_logic; signal en_1_in_2 : std_logic; signal en_1_in_8 : std_logic; process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; -- Defaut enables to 0 en_1_in_16 <= '0'; en_1_in_2 <= '0'; en_1_in_8 <= '0'; if cnt = 0 then en_1_in_16 <= '1'; end if; if cnt rem 2 = 0 then en_1_in_2 <= '1'; end if; if cnt rem 8 = 0 then en_1_in_8 <= '1'; end if; end if; end process;
process(CLK_50)
begin
if rising_edge(CLK_50) then
cnt <= cnt + 1;
--25MHz
if cnt rem 1 = 0 then
CLK_25 <= NOT(CLK_25);
end if;
--5MHz
if cnt rem 5 = 0 then
CLK_5 <= NOT(CLK_5);
end if;
--1MHz
if cnt rem 25 = 0 then
CLK_1 <= NOT(CLK_1);
end if;
--Reset
if(cnt>49)then
cnt<="000001";
end if;
end if;
end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 architecture rtl of clk_divn is signal pos_count, neg_count : unsigned(count_size-1 downto 0); begin pos_cnt_proc : process(clk_in) is begin if rising_edge(clk_in) then if rst='1' then pos_count <= (others => '0'); else if pos_count = div-1 then pos_count <= (others => '0'); else pos_count <= pos_count + 1; end if; end if; end if; end process; neg_cnt_proc : process(clk_in) is begin if falling_edge(clk_in) then if rst='1' then neg_count <= (others => '0'); else if neg_count = div-1 then neg_count <= (others => '0'); else neg_count <= neg_count + 1; end if; end if; end if; end process; clk_out <= '1' when (pos_count > (div/2)) OR (neg_count > (div/2)) else '0'; end architecture rtl;
process(CLK_50)
begin
if rising_edge(CLK_50) then
if cnt >= n then
SPI_Ena = 1
cnt = 0
else
SPI_Ena = 0
cnt <= cnt + 1;
endif
end if;
end process;
process(SPI)
begin
if rising_edge(CLK_50) then (this is the system clock)
if SPI_ENA then (and this is the ENABLE for processing SPI signals)
SCK = <= NOT(SCK);
...here do the other SPI processes... (FSM to write MOSI, read MISO, count the bits, maybe control !CS...)
end if;
end if;
end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PROCESS(clk,reset) BEGIN IF reset = '1' THEN bitcnt <= 0; nCS_DAC <= '1'; DACCLK <= '0'; ELSIF rising_edge(clk) THEN IF clkcnt > 0 THEN clkcnt <= clkcnt - 1; END IF; CASE bitcnt IS WHEN 0 => DACCLK <= '0'; IF start = '1' AND clkcnt = 0 THEN sr <= data; nCS_DAC <= '0'; bitcnt <= 8; clkcnt <= 15; END IF; WHEN OTHERS => -- SPI frequency = input frequency/16, 50% duty cycle IF clkcnt = 8 THEN DACCLK <= '1'; ELSIF clkcnt = 0 THEN clkcnt <= 15; sr <= sr(6 downto 0) & "0"; DACCLK <= '0'; bitcnt <= bitcnt - 1; IF bitcnt = 1 THEN nCS_DAC <= '1'; END IF; END IF; END CASE; END IF; END PROCESS; MOSI <= sr(7);
So Klaus, what you were telling to me on the I2C thread is what we are discussing on this one, isn't it?
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