PROM to FPGA CONFIGURATION

[Navya]

spartan 3 family configuration datasheet

Hi All,
I have read from spartan and platform flash data sheet that ,"in master serial mode, FPGA automatically loads the configuration bitstream in bit serial from external memory synchronized by the configuration clock(CCLK) generated by the FPGA"

I want to know if there is any specific program inside the PROM or FPGA to identify the clk and give corresponding data to FPGA. How is it happening automatically?

Is master serial mode or master parallel mode faster in case of Spartan 3 series?

Please reply urgently,

Thanks

 

[bis_]

master serial prom configuration spartan

Full and detailed description, with all required connections, of this mode of configuration (an all another modes) you can find on the Xilinx Web site. inside doccument named "Spartan-3 Generation Configuration User Guide" UG332.pdf. If you are too lazy to search I have palce direct link for that.
**broken link removed**

bis

 

[Navya]

prom is configuration master

Thanks bis. But can u tell me where can i find master parallel mode using platform flash PROM design as master serial in this document.

 

[bansalr]

fpga configuration modes

U can find in the FPGA data sheet under configuration section.

 

[bis_]

fpga prom

Read Chapter 6 of the UG332.pdf:

Master Parallel Mode is only available on the Spartan-3 FPGA family. See the
DS099: Spartan-3 FPGA Family Data Sheet for details.

and find document DS099 at the xilinx web.
**broken link removed**
Read part named Configuration/Configuration Modes.

bis