PROm programming issue

[Navya]

we did the testing in Xilinx ISE with XC3s1500 using the PCI core which we had modified
In that "Total equivalent gate count for design = 747,282 " and "Additional JTAG gate count for IOBs = 4,176" .If this is the total number of gates utilized by our code, then will XC3s400 be sufficient to run this same code?

 

[bis_]

Simple gate counting is only for estimation of possibilities. But XC3s400 has gate index 400K, Your design requires about 750K gates. There is very small or none chance to implement it into XC3s400. (Remember about differences in device package/pin-count options between devices, look at DS099 document) But it is very simple to test this. Change the device in your project and try to fit them.

bis

 

[Navya]

Hi bis,
i would like to clarify that ur conclusion is wrong the same code can be downloaded to fpga with 400 gates. we were sucessful in downloading the same bit file. The total equivalent gate count have no connection with the ip core, it varies accordingly..

 

[bansalr]

As per my understanding Equivalent gate count amounts to total gate count for Logic + memory.

1500 Device will have 1500K equivalnet gate count as logic implemented in CLB and memory will be extra. that's why u r able to fit the design in 400.

comparing across fpga's use LUT's and BRAM utilization for fitting not logic count. i.e. an indicative figure for ASIC equivalent.