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project :Gray Counter

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bianca_p

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Hi , I'm trying to make a digital circuit that implements a 5-bit Gray code counter with priority reset. I've tried simulating the circuit on ISP lever Classic Project and doesn't work.I have to use GALp16v8 :(
I have the following errors:

Input file: 'gray.tt2'
Device 'p16v8'
Note 4161: Using device architecture type P16V8R.
Warning 4034:Unable to preserve preassignments - performing second pass without preassignments.
Note 4059: Signal Q0 cannot be assigned (to pin 16) because
there are too many terms for output Q0 pin 16.

Note 4046: Signal Q1 (which has no OE) has been
assigned to pin 15 (which has pin OE).
Note 4046: Signal Q2 (which has no OE) has been
assigned to pin 14 (which has pin OE).
Note 4046: Signal Q3 (which has no OE) has been
assigned to pin 13 (which has pin OE).
Note 4046: Signal Q4 (which has no OE) has been
assigned to pin 12 (which has pin OE).
Design does NOT fit

FIT complete. Time: 1 second.

Done: failed with exit code: 0001.

Code:
Code: 
MODULE Numarator_Gray

TITLE 'Numarator_Gray_5_biti'

declarations

clock,reset pin 1,2;
Y pin 3;
Q0,Q1,Q2,Q3,Q4  pin 14,15,16,17,18 istype 'reg';



"definitiile starilor

	QSTATE=[Q4,Q3,Q2,Q1,Q0];
	S0=[0,0,0,0,0];
	S1=[0,0,0,0,1];
	S2=[0,0,0,1,1];
	S3=[0,0,0,1,0];
	S4=[0,0,1,1,0];
	S5=[0,0,1,1,1];
	S6=[0,0,1,0,1];
	S7=[0,0,1,0,0];
	S8=[0,1,1,0,0];
	S9=[0,1,1,0,1];
	S10=[0,1,1,1,1];
	S11=[0,1,1,1,0];
	S12=[0,1,0,1,0];
	S13=[0,1,0,1,1];
	S14=[0,1,0,0,1];
	S15=[0,1,0,0,0];
	S16=[1,1,0,0,0];
	S17=[1,1,0,0,1];
	S18=[1,1,0,1,1];
	S19=[1,1,0,1,0];
	S20=[1,1,1,1,0];
	S21=[1,1,1,1,1];
	S22=[1,1,1,0,1];
	S23=[1,1,1,0,0];
	S24=[1,0,1,0,0];
	S25=[1,0,1,0,1];
	S26=[1,0,1,1,1];
	S27=[1,0,1,1,0];
	S28=[1,0,0,1,0];
	S29=[1,0,0,1,1];
	S30=[1,0,0,0,1];
	S31=[1,0,0,0,0];

equations
@dcset;
	QSTATE.clk=clock;
	when ( Y==1 ) then {
	             when (reset == 0) then QSTATE := S0;
		else when (QSTATE == S0) THEN QSTATE := S1;
		else when (QSTATE == S1) THEN QSTATE := S2;
		else when (QSTATE == S2) THEN QSTATE := S3;
		else when (QSTATE == S3) THEN QSTATE := S4;
		else when (QSTATE == S4) THEN QSTATE := S5;
		else when (QSTATE == S5) THEN QSTATE := S6;
		else when (QSTATE == S6) THEN QSTATE := S7;
		else when (QSTATE == S7) THEN QSTATE := S8;
		else when (QSTATE == S8) THEN QSTATE := S9;
		else when (QSTATE == S9) THEN QSTATE := S10;
		else when (QSTATE == S10) THEN QSTATE := S11;
		else when (QSTATE == S11) THEN QSTATE := S12;
		else when (QSTATE == S12) THEN QSTATE := S13;
		else when (QSTATE == S13) THEN QSTATE := S14;
		else when (QSTATE == S14) THEN QSTATE := S15;
		else when (QSTATE == S15) THEN QSTATE := S16;
		else when (QSTATE == S16) THEN QSTATE := S17;
		else when (QSTATE == S17) THEN QSTATE := S18;
		else when (QSTATE == S18) THEN QSTATE := S19;
		else when (QSTATE == S19) THEN QSTATE := S20;
		else when (QSTATE == S20) THEN QSTATE := S21;
		else when (QSTATE == S21) THEN QSTATE := S22;
		else when (QSTATE == S22) THEN QSTATE := S23;
		else when (QSTATE == S23) THEN QSTATE := S24;
		else when (QSTATE == S24) THEN QSTATE := S25;
		else when (QSTATE == S25) THEN QSTATE := S26;
		else when (QSTATE == S26) THEN QSTATE := S27;
		else when (QSTATE == S27) THEN QSTATE := S28;
		else when (QSTATE == S28) THEN QSTATE := S29;
		else when (QSTATE == S29) THEN QSTATE := S30;
		else when (QSTATE == S30) THEN QSTATE := S31;
		else when (QSTATE == S31) THEN QSTATE := S0;
	}
	else
		{
		     when (reset == 0) then QSTATE := S0;
		else when (QSTATE == S0) THEN QSTATE := S31;
		else when (QSTATE == S31) THEN QSTATE := S30;
		else when (QSTATE == S30) THEN QSTATE := S29;
		else when (QSTATE == S29) THEN QSTATE := S28;
		else when (QSTATE == S28) THEN QSTATE := S27;
		else when (QSTATE == S27) THEN QSTATE := S26;
		else when (QSTATE == S26) THEN QSTATE := S25;
		else when (QSTATE == S25) THEN QSTATE := S24;
		else when (QSTATE == S24) THEN QSTATE := S23;
		else when (QSTATE == S23) THEN QSTATE := S22;
		else when (QSTATE == S22) THEN QSTATE := S21;
		else when (QSTATE == S21) THEN QSTATE := S20;
		else when (QSTATE == S20) THEN QSTATE := S19;
		else when (QSTATE == S19) THEN QSTATE := S18;
		else when (QSTATE == S18) THEN QSTATE := S17;
		else when (QSTATE == S17) THEN QSTATE := S16;
		else when (QSTATE == S16) THEN QSTATE := S15;
		else when (QSTATE == S15) THEN QSTATE := S14;
		else when (QSTATE == S14) THEN QSTATE := S13;
		else when (QSTATE == S13) THEN QSTATE := S12;
		else when (QSTATE == S12) THEN QSTATE := S11;
		else when (QSTATE == S11) THEN QSTATE := S10;
		else when (QSTATE == S10) THEN QSTATE := S9;
		else when (QSTATE == S9) THEN QSTATE := S8;
		else when (QSTATE == S8) THEN QSTATE := S7;
		else when (QSTATE == S7) THEN QSTATE := S6;
		else when (QSTATE == S6) THEN QSTATE := S5;
		else when (QSTATE == S5) THEN QSTATE := S4;
		else when (QSTATE == S4) THEN QSTATE := S3;
		else when (QSTATE == S3) THEN QSTATE := S2;
		else when (QSTATE == S2) THEN QSTATE := S1;
		else when (QSTATE == S1) THEN QSTATE := S0;
		}

Test_Vectors  ([reset,clock,Y]->[Q4,Q3,Q2,Q1,Q0])
               [0, .c., .x.]->[0,0,0,0,0];
               [1, .c.,  1 ]->[0,0,0,0,1];
               [1, .c.,  1 ]->[0,0,0,1,1];
               [1, .c.,  1 ]->[0,0,0,1,0];
               [1, .c.,  1 ]->[0,0,1,1,0];
               [1, .c.,  1 ]->[0,0,1,1,1];
               [1, .c.,  1 ]->[0,0,1,0,1];
               [1, .c.,  1 ]->[0,0,1,0,0];
               [1, .c.,  1 ]->[0,1,1,0,0];
               [1, .c.,  1 ]->[0,1,1,0,1];
               [1, .c.,  1 ]->[0,1,1,1,1];
               [1, .c.,  1 ]->[0,1,1,1,0];
               [1, .c.,  1 ]->[0,1,0,1,0];
               [1, .c.,  1 ]->[0,1,0,1,1];
               [1, .c.,  1 ]->[0,1,0,0,1];
               [1, .c.,  1 ]->[0,1,0,0,0];
               [1, .c.,  1 ]->[1,1,0,0,0];
               [1, .c.,  1 ]->[1,1,0,0,1];
               [1, .c.,  1 ]->[1,1,0,1,1];
               [1, .c.,  1 ]->[1,1,0,1,0];
               [1, .c.,  1 ]->[1,1,1,1,0];
               [1, .c.,  1 ]->[1,1,1,1,1];
               [1, .c.,  1 ]->[1,1,1,0,1];
               [1, .c.,  1 ]->[1,1,1,0,0];
               [1, .c.,  1 ]->[1,0,1,0,0];
               [1, .c.,  1 ]->[1,0,1,0,1];
               [1, .c.,  1 ]->[1,0,1,1,1];
               [1, .c.,  1 ]->[1,0,1,1,0];
               [1, .c.,  1 ]->[1,0,0,1,0];
               [1, .c.,  1 ]->[1,0,0,1,1];
               [1, .c.,  1 ]->[1,0,0,0,1];
               [1, .c.,  1 ]->[1,0,0,0,0];

END
 
Last edited by a moderator:

bianca_p said:
Note 4059: Signal Q0 cannot be assigned (to pin 16) because
there are too many terms for output Q0 pin 16.
Click to expand...
There are too many terms required to generate the Q0 output.

It's been many decades since I used a 16v8 but I recall the most terms were in the middle pins, which is where the fitter decided to put the Q0 output as it wouldn't have fit in the original pin 14 location, but unfortunately there are still too many terms for it to fit on pin 16.

You require a part that has more terms.
 

Thanks for your reply.
There is no other way? ( Only 16v8 I must use)
 

Perhaps there is a non-standard gray sequence that would use less terms, but I doubt it. The problem is the number of terms required by all the sequences of 2 1's followed by 2 0's they end up as a pretty sparse Karnaugh map, which means a lot of terms.

why do you need to do this conversion in the first place?
and why in an antiquated (and obsolete) 16v8 part?

Took a look at the datasheet and it reminded me you could use the output feedback and generate part of the equation terms using one pin and feed the output back into the array to generate the rest of the terms combined with the first pins terms, this will double the Tpd of the output, but would allow the design to fit. This will only work if you have spare output pins (which it looks like you do).

You might have to compute the terms manually instead of using the high level language tools. I regularly did this using palasm back in the 'old days'.
 

ads-ee said:
There are too many terms required to generate the Q0 output.

You require a part that has more terms.
Click to expand...
That's the way I remember it, too: that some of the outputs had fewer product-term inputs than others.
But I can't find a data-sheet on line that shows that: they all have seven inputs, which should be enough.
Maybe the tool in use can be targeted to a slightly-different PAL/GAL.
 
Last edited:

It has 8 terms on pins 15 & 16 (no feedback), but I'm pretty sure that you need 16 terms for a 5-bit gray counter the 4-bit gray counter has 8 terms for Q0. The 1's or 0's are in a checkerboard pattern.

Actually I think you'll have to use 3 pins to do this function as you need to use a term to get the feedback, which eats up one term and the pins have either 7 or 8 terms. So maybe 2 7 term equations followed by a 3 term equation, which combines the two other outputs into the final Q0 output.
 

I have to make a project (to implement a 5-bit Gray code counter with priority reset) . And this is the only GAL we use.

You lost me with your explication.
 

bianca_p said:
I have to make a project (to implement a 5-bit Gray code counter with priority reset) . And this is the only GAL we use.

You lost me with your explication.
Click to expand...
what part of my explanation?

Have you looked over the Gal16v8 datasheet I linked? each of the horizontal lines corresponds to a product term.

So pins 15 & 16 have 8 product terms, the rest of the pins have 7 product terms if there is feedback and 8 without feedback. That's what all the diagrams are for of the macrocell options.

As there is feedback from an output pin you can use two pins to create the product terms for 7 terms on one pin 7 terms on another pin and combine the last 2 terms and the 2 other output feedback results using a third pin. That third pin will be the output Q0. If you draw out the karnaugh map of Q0 you'll find it turns out to be a checkerboard pattern that's why it doesn't fit and the other outputs do.
 

It's too much for me what you said.
It's hard. I don't know how to resolve it.

- - - Updated - - -

@ads-ee Can you help me to write code?
 

I noticed you also have a thread posted here.

I'm not sure how much logic design experience you have, but I'm beginning to suspect it's not much.

Do you know how to generate the karnaugh maps for each bit of your output gray code?

I'm not sure what the code you gave is written in, but it's not palasm/VHDL/Verilog, so I'm not going to be able to help code the equations, but you'll need to understand the equations that you are coding and that would come from the K-maps.

Q0 of a 3-bit gray code would end up like so:
Code: 
[FONT=Courier New]Three bit binary to gray code:
000 | 00 0
001 | 00 1
010 | 01 1
011 | 01 0
100 | 11 0
101 | 11 1
110 | 10 1
111 | 10 0
         ^ K-map for this column:
Q0:
 D\ 0 
2 1\  0 | 1
----+---+---
0 0 | 0 | 1
0 1 | 1 | 0
1 1 | 0 | 1
1 0 | 1 | 0

Q0 := /D2*/D1*D0 + /D2*D1*/D0 + D2*D1*D0 + D2*/D1*/D0[/FONT]

as can bee seen the k-map ends up as a checkerboard pattern, which requires 4 terms for a 3-bit (8 counts) so in your case the Q0 output requires (5-bit=32 counts) 16 terms, which doesn't fit in the 8 term equation capability of the 16V8

So my suggestion was to split the terms into different outputs.
Code: 
suppose the above equation has to be implemented using 2 term equations.

T0 := /D2*/D1*D0 + /D2*D1*/D0
T1 := D2*D1*D0 + D2*/D1*/D0
Q0 := T0 + T1
 
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