Code VHDL - [expand]
[syntax=vhdl]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
entity tb_si4136 is
end entity ;
--------------------------------------------------------------------------------
architecture Bhv of tb_si4136 is
-----------------------------
-- Port Signals
-----------------------------
signal clk : std_logic := '1';
signal rst_n : std_logic;
signal data : std_logic_vector(17 downto 0);
signal add : std_logic_vector(3 downto 0);
signal go : std_logic;
signal sent : std_logic;
signal SE_N : std_logic;
signal SDATA : std_logic;
signal SCLK : std_logic;
begin -- architecture Bhv
-----------------------------
-- component instantiation
-----------------------------
si4136_INST: entity work.si4136
port map (
clk => clk,
rst_n => rst_n,
data => data,
add => add,
go => go,
sent => sent,
SE_N => SE_N,
SDATA => SDATA,
SCLK => SCLK);
clk <= not clk after 5 ns;
rst_n <= '0','1' after 1 us;
StimuliProcess : process
begin
go <= '0';
wait until rst_n = '1';
l_i : for i in 1 to 100 loop
wait until rising_edge(clk);
end loop l_i;
add <= b"0101";
data <= b"101010101010101010";
go <= '1';
--
wait until rising_edge(clk);
go <= '0';
wait until sent = '1';
report "sent data with address";
wait;
end process StimuliProcess;
end architecture Bhv;
[/SYNTAX][syntax=c]
static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
{
adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,SI4126_MAIN_XINDIV2);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
SI4126_POWERDOWN_PDIB |
SI4126_POWERDOWN_PDRB);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,(chan == 14 ?2110 : (2033 + (chan * 5))));
adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
}
[/syntax]
rocessrocessHI.I simulated the first code but when I generate testbench for si4136:
ENTITY testbenchsi4136 IS
END testbenchsi4136;
ARCHITECTURE behavior OF testbenchsi4136 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT si4136
PORT(
clk : IN std_logic;
rst_n : IN std_logic;
data : IN std_logic_vector(17 downto 0);
add : IN std_logic_vector(3 downto 0);
go : IN std_logic;
sent : OUT std_logic;
SE_N : OUT std_logic;
SDATA : OUT std_logic;
SCLK : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal rst_n : std_logic := '0';
signal data : std_logic_vector(17 downto 0) := (others => '0');
signal add : std_logic_vector(3 downto 0) := (others => '0');
signal go : std_logic := '0';
--Outputs
signal sent : std_logic;
signal SE_N : std_logic;
signal SDATA : std_logic;
signal SCLK : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant SCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: si4136 PORT MAP (
clk => clk,
rst_n => rst_n,
data => data,
add => add,
go => go,
sent => sent,
SE_N => SE_N,
SDATA => SDATA,
SCLK => SCLK
);
-- Clock process definitions
clk_process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
SCLK_process
begin
SCLK <= '0';
wait for SCLK_period/2;
SCLK <= '1';
wait for SCLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
this code have this error:
ERROR: The Top module has not been specified. This can happen if no sources have been added to the project,
best regards.
