programming fpga by JTAG WITH VHDL CODE

[gaffarnazari@yahoo.com]

HI TO ALL.
in the first:
I write this vhdl code for fpga with xin=10mhz

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity spi1 is
    Port ( clk : in  STD_LOGIC; --100 Mhz
            SO :out std_logic;  --lsfr out
              rst_n : in std_logic;
             Go : inout std_logic ;
              SE_N : out std_logic := '1';
              SDATA : out std_logic := '0';
              SCLK : INout std_logic;
              pn :out std_logic := '1';
              led:out std_logic_vector(6 downto 0):="0000000"
                       );
end spi1;
 
architecture Behavioral of nikkar_spi1 is
 
type write_vec is array (9 downto 1) of std_logic_vector(21 downto 0) ;
signal wire_send_spi:write_vec;
signal reg_send_spi : std_logic_vector(21 downto 0) := (others => '0');
signal reg_cnt_data : integer range 0 to 31 := 21;
type type_sm_send_spi is (IDLE,RCV_GO,SEND,ENDED,waiting);
signal sm_send_spi : type_sm_send_spi;
signal dataNum :integer range 1 to 9:=1;
signal sendStart  :std_logic := '1';
signal data:integer range 1 to 3;
signal sendEnd :std_logic := '1';
signal count1 : integer range 1 to 10000000:=1;    ---delay 1s
 
begin
pn<='1';
process(clk,rst_n)
 
begin
if(rst_n = '0') then
 
sendStart<='0';
    elsif (clk' event and clk='0') then
 
 
case data is
 
    when 1 =>
sendStart<='1';
        wire_send_spi(1)<="0000110000000010000000";  
        wire_send_spi(2)<="0000000000000101000001";  
        wire_send_spi(3)<="0000000000000000110010"; 
        wire_send_spi(4)<="0000000000000000000011";  
        wire_send_spi(5)<="0000001111110100100100";   
        wire_send_spi(6)<="0000000000000000000101"; 
        wire_send_spi(7)<="0000000000000000000110";
        wire_send_spi(8)<="0000000000010100000111";  
        wire_send_spi(9)<="0000000000001100101000";  
        if(sendEnd='1')then
        sendStart<='0';
        end if;
when 2 =>
        sendStart<='1';
                    wire_send_spi(1)<="0000110000000000000000"; 
                    wire_send_spi(2)<="0000000000001010010001";  
        wire_send_spi(3)<="0000000000000000010010"; 
        wire_send_spi(4)<="0000000000000000000011"; 
        wire_send_spi(5)<="0000010000000001000100";   
        wire_send_spi(6)<="0000000000000000000101";   
        wire_send_spi(7)<="0000000000000000000110";    
        wire_send_spi(8)<="0000000000010100000111";    
        wire_send_spi(9)<="0000000000000000001000";    
        if(sendEnd='1')then
            sendStart<='0';
            
 end if;
when 3 =>
    sendStart<='1';
              wire_send_spi(1)<="0000110000000000000000";
              wire_send_spi(2)<="0000000000001010010001";   
     wire_send_spi(3)<="0000000000000000010010";  
     wire_send_spi(4)<="0000000000000000000011"; 
    wire_send_spi(5)<="0000010000001101100100";   
    wire_send_spi(6)<="0000000000000000000101";       
             wire_send_spi(7)<="0000000000000000000110";
    wire_send_spi(8)<="0000000000010100000111";    
           wire_send_spi(9)<="0000000000000000001000";    
        if(sendEnd='1')then
            sendStart<='0';
    end if;
when others =>  
    end case;
 
end if; 
 
end process;
 
 
SCLK<=clk;
    
 
process(SCLK,rst_n) is
begin
 
if (rst_n = '0') then
    SE_N <= '1';
    SDATA <='0';
    sm_send_spi<=IDLE;
    sendEnd<='0';
elsif(SCLK' event and SCLK='0')then
 
    case sm_send_spi is
----------------------------------------------------------------------------------------------
    when IDLE =>
        
        SE_N <= '1';
        SDATA <= '0';
        sendEnd<='0';
        dataNum<=1;
        if (sendStart ='1') then 
Go<='0';            
            reg_send_spi <= wire_send_spi(dataNum);
            sm_send_spi <= rcv_go;
        
        end if;
---------------------------------------------------------------------------------------     
    when RCV_GO =>
 
        SE_N <= '0';
        reg_cnt_data<=21;
        SDATA <= reg_send_spi(21);
        --------------
        
        sm_send_spi <= SEND;    
        
--------------------------------------------------------------------------------------------------------        
    when SEND =>
       led(6) <='0';
if (reg_cnt_data > 0) then
            SDATA <= reg_send_spi(reg_cnt_data-1);
            reg_cnt_data <= reg_cnt_data - 1;
        else
            SE_N <= '1';
            dataNum<=dataNum+1;
            sm_send_spi <= ENDED;   
        end if;
-------------------------------------------------------------------------------     
    when ENDED =>
 
        if(dataNum=10)then
            sm_send_spi <=waiting;
            Go<='1';
            sendEnd<='1';
        else
            reg_send_spi <= wire_send_spi(dataNum);
            sm_send_spi <= RCV_GO;      
    end if;
-----   ------------------------------------------------------------------------------
    when waiting => 
 
           led(6) <='1';
if(count1=10000000)then
    sm_send_spi <=IDLE;
if(data=4)then
        data<=1;
        else
            data <=data+1;
            
            
    end if;     
    count1 <=1;
else
    count1 <=count1+1;
    led (5 downto 0) <= conv_std_logic_vector(data,6);
    end if;
    
    end case;
end if; 
    
end process;
-------------------------------------------------

---

and my problem :
WHEN I simulated this code the led's dont turn on in type of waiting
because I WRITE CODE FOR 1s delay but on the my board I see only signal data=1
why I cant see data=2 and 3 when I PROGRAMMING code on fpga board and how I CAN SEE IN THIS case on led's?
for 1S delay: COUNT1=10000000 WITH XIN OF FPGA ON THE BOARD IS EQUAL=10MHZ
THANK YOU

 

[ads-ee]

HI TO ALL.
in the first:
I write this vhdl code for fpga with xin=10mhz

and my problem :
WHEN I simulated this code the led's dont turn on in type of waiting
because I WRITE CODE FOR 1s delay but on the my board I see only signal data=1
why I cant see data=2 and 3 when I PROGRAMMING code on fpga board and how I CAN SEE IN THIS case on led's?
for 1S delay: COUNT1=10000000 WITH XIN OF FPGA ON THE BOARD IS EQUAL=10MHZ
THANK YOU

Your question is unclear, where is xin in your code? Is that a signal on the schematic is it the same as the clk port?

Are you having problems with simulation or on hardware after implementing the design? You mention both simulated and programming code on the board.

Are you sure you have the XIN pin specified for clk in your constraints?

The following looks wrong, I might be mistaken, but I don't think you can use a value outside the range specified.

signal data:integer range 1 to 3;
-- You're comparing data with 4, which is outside the range in the declaration?
    if(data=4)then
        data<=1;
    else
        data <=data+1;
    end if;

 

[gaffarnazari@yahoo.com]

--excuse me data is equal=3 I MISTAKE THERE.
my problem is I cant see type of when( 2 and 3) on ouput on hardware(fpga board) I only see type of when 1
and other problem I assign led<=conv_std_logic_vector(data,6) but I CANT see it on out put on board(by led's) ( my delay is equal 1s)
how can I SEE my data on led's on the board?(what is that code?)
thank you