kevinj
Advanced Member level 4
Hi,
I'm using Verilog to create an ASIC and then later using Encounter to synthesize the design. In Verilog I use a Block ROM to store some coefficients, however for the ASIC I would like to stream in the coefficients as those values change from one ASIC to the other. I'm thinking about using some sort of SPI interface. Is there a simple way of achieving this? Or how would I go about doing this? I'm targeting this design for UMC 90nm.
Thanks
I'm using Verilog to create an ASIC and then later using Encounter to synthesize the design. In Verilog I use a Block ROM to store some coefficients, however for the ASIC I would like to stream in the coefficients as those values change from one ASIC to the other. I'm thinking about using some sort of SPI interface. Is there a simple way of achieving this? Or how would I go about doing this? I'm targeting this design for UMC 90nm.
Thanks