rp0777
Newbie level 2
Hi,
I'm having this problem where my processor, S3C2440, can only access 50% of the memory on each of my two SDRAM modules, HY57V561620. I've double checked my schematic and everything's good. So I think the issue may have to do with the layout. However, from what I know, if all the wires are routed/connected properly, decoupling capcitors are correctly placed, and DRC passed then that means layout is good. Is that correct or am I missing something?
Anyways, any suggestions on what I can do to debug this or where I can look? I'm trying to avoid using the oscilloscope and logic analyzer.
If someone has knowledge of S3C2440 and would like to see the schematic/layout, I can have them forwarded.
Any help would be appreciated.
Thanks.
I'm having this problem where my processor, S3C2440, can only access 50% of the memory on each of my two SDRAM modules, HY57V561620. I've double checked my schematic and everything's good. So I think the issue may have to do with the layout. However, from what I know, if all the wires are routed/connected properly, decoupling capcitors are correctly placed, and DRC passed then that means layout is good. Is that correct or am I missing something?
Anyways, any suggestions on what I can do to debug this or where I can look? I'm trying to avoid using the oscilloscope and logic analyzer.
If someone has knowledge of S3C2440 and would like to see the schematic/layout, I can have them forwarded.
Any help would be appreciated.
Thanks.
