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process independent High Speed clock delays in sub nseconds

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gilbertomaldito

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Hi,

I will be needing clock delays fpr my SerDes design. At first I used inverter buffers for the clock delays on my SerDes, however, these delays are vulnerable to process variation. The delays I needed are sub nanoseconds like 0.1ns. How can I possibly acquire the delay with such independence on process?

Please Help :D

--andrew
 

JoannesPaulus

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The delays are surely process dependent (shorter for fast process and longer for slow process) but everything is affected the same way. So, if you design your timing correctly, you should not see any problem.

If you really need an absolute delay, the best way is to use a calibrated RC delay, but that is not easy to implement for sub-ns delays...
 

AdvaRes

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Re: process independent High Speed clock delays in sub nseco

Hi,
Actually I'm facing the same problem but with also temperature and Voltage variation. For both clock and signals I used buffer.
Do somebody know how to design that can maintain their intrinsic delay stable if T or V change ?
 

dick_freebird

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You need either an ECL-like approach (low swing logic
with an excess of speed, current controlled for a flat delay
tempco and low process sensitivity), like SCL or CML
in CMOS, or you need a too-fast inverter current starved
with a closed loop control that can null process, temp,
line, etc. If you had a reference clock then you could
loop-lock an inverter chain to that and get the reference
to use for the delay buffers. If (say) you were just looking
to put the clock in the eye, you'd lock a 17-stage ring
oscillator to the data edges and tap your clock off the
9th, or something like that. Unless you have to deal with
burst mode, which can be more "interesting".
 

gilbertomaldito

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Re: process independent High Speed clock delays in sub nseco

dick_freebird said:
You need either an ECL-like approach (low swing logic
with an excess of speed, current controlled for a flat delay
tempco and low process sensitivity), like SCL or CML
in CMOS, or you need a too-fast inverter current starved
with a closed loop control that can null process, temp,
line, etc. If you had a reference clock then you could
loop-lock an inverter chain to that and get the reference
to use for the delay buffers. If (say) you were just looking
to put the clock in the eye, you'd lock a 17-stage ring
oscillator to the data edges and tap your clock off the
9th, or something like that. Unless you have to deal with
burst mode, which can be more "interesting".

Hi freebird,

I appreciate your suggestions, but its still not clear to me. Can you help me out?
Attached is my SerDes circuit. I am using tree type for both serializer and deserializer. For each level, I will be needing different frequencies of clock. I also be needing the exact delays for each of these clocks relative to each other for my SerDes to work properly.

Here are my questions.

1. For my application, what do you think is the best way to achieve a process independent delays for delays A to H.

2. WHen my serializer is active, I still need to use the clock coming from the data-strobe clock recovery circuit, so how can I synchronize my clock from my clock recovery to my logical side block?

3. Do you have a better suggestion on how to implement SerDes?

thank you

--andrew
 

JoannesPaulus

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Andrew,
just one comment: your datapath is most likely a chain of FFs or latches that will "zero" the delay of whatever you put in between them. You can take advantage of this by having synchronous dividers for your clock path. The delay variations over PVT will affect both the clock and the datapath.

Maybe I am missing something but I really do not recommend you to try to have a PVT-independent delay... just live with it.
 

gilbertomaldito

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Hi JoannesPaulus,

thank you very much for the information.
My PHY should support both isochronous and asynchronous data transmission. Is it ok to use a synchronous clock divider?

Do you have papers that discuss about synchronous clock dividers?

--andrew
 

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