I design currently in 65nm CMOS. I typically run TT, FF, SS, FS, and SF corners. The letters represent the drive strength of the NMOS and PMOS transistors. For example, a "FS" corner means Fast NMOS and Slow PMOS. At each corner, data is loaded from the manufacturer that describes different
global variations(i.e. all devices affected the same) for the transistor. There are many different process variables that change ... it depends on the manufacturer of course. You need to look at the corner files to see what changes and gives the biggest impact on the transistors.
Of course if you are designing in a newer digital process it is essential that you run Monte-Carlo simulations at each process corner. This ensures that you take into account all
local variations (i.e. each transistor has a different drive strength mostly to the distribution of Vt).
Cheers
analogLow