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process confirm, 0.35um technology?

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lhlblue

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i saw a strange process(CMOS technology):
2P2M process, and the minimum poly width Lmin=0.35um, and the contact size=0.35um also, please tell me which foundry will this be? TSMC? UMC? SMIC? etc...
thanks.
 

... the minimum poly width Lmin=0.35um, and the contact size=0.35um also

I think min. poly width is valid for gates and wires without contact only. Where you put contacts, you'd probably have to widen the poly.

Usually poly to contact overlap is necessary for 0.35µm processes. See here an Assura DRC rules' example for such a process:

Code:
drc( CCON width < 0.35 "small CCON   < 0.35, # 701(1601)" )
drc( CCON 0.1225 < area "big CCON area > 0.1225, # 701(1601)" )

	polycont = geomAnd( CCON CPOL )

drc( CPOL polycont enc < 0.21 "overlap of CPOL over CCON < 0.21, # 705(1604)" )

So for a poly contact here you need a min. poly width of 0.77µm.
 

Double poly means a mixed signal process (POP cap)
and the rest of it just looks like a 10-year-old (or more)
standard CMOS feature size. Probably still in production
at many foundries in similar form, but probably not
being promoted for new designs with any great emphasis.
 

hi, dick_freebird, what do you mean by 'a 10-year-old (or more)
standard CMOS feature size'? and which foundry may it be?
thanks.
 

TowerJazz CA35 (running at Rockwell fab before Jazz
owned it)? Something of that sort. 0.35um is a good
node for analog at 3.3V-ish.
 

TowerJazz CA35 (running at Rockwell fab before Jazz
owned it)? Something of that sort. 0.35um is a good
node for analog at 3.3V-ish.



TowerJazz CA35 is a CMOS or BiCMOS technology? and can you give me some detailed information about it?
i cannot search related information on internet.
 

The base process has many variants / branches and
some include BJTs. You should try and find the info
on their web site, although they do not give as much
effort to that generation as they do the newer CA18/
SBC18 flow.
 

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