Vonn
Full Member level 4
c@dence
Hi every body, Iam trying to simulate my verilog code using c@adence tools .. when I tried to use Veril0g-XL .. it works well for a single module but I faced a problem with my Hierarchical Design ..the tool can't see the nested components and there is an error (module or primitive not defined verilog-MPND) ... ok how to define them ? I put all my files in the same directory as I used to do with X!l!n!x ... my code is working with X!l!n!x but because Iam new to c@adence I just don't know how to make the tool to see the other components in the Hierarchical Design ?
any body can give me a hand ... thanx
Hi every body, Iam trying to simulate my verilog code using c@adence tools .. when I tried to use Veril0g-XL .. it works well for a single module but I faced a problem with my Hierarchical Design ..the tool can't see the nested components and there is an error (module or primitive not defined verilog-MPND) ... ok how to define them ? I put all my files in the same directory as I used to do with X!l!n!x ... my code is working with X!l!n!x but because Iam new to c@adence I just don't know how to make the tool to see the other components in the Hierarchical Design ?
any body can give me a hand ... thanx