ywguo
Junior Member level 2
Hi,
I am designing a small chip. Now I have two versions, one with scan chain, and the other NOT.
When I generate clock tree in P&R tools, like Astro, it gives short path delay (~3ns) and small skew (0.111ns) for the design w/o scan chain, while very long path delay (~16ns) and big skew (~2ns) for the design with scan chain.
I have inserted gated clock in my design to reduce power consumption. The report show that there are more MUXs and buffers along the clock tree for the design with scan chain.
Should I avoid gated clock?
Can anybody help me?
Thanks
Yawei Guo
I am designing a small chip. Now I have two versions, one with scan chain, and the other NOT.
When I generate clock tree in P&R tools, like Astro, it gives short path delay (~3ns) and small skew (0.111ns) for the design w/o scan chain, while very long path delay (~16ns) and big skew (~2ns) for the design with scan chain.
I have inserted gated clock in my design to reduce power consumption. The report show that there are more MUXs and buffers along the clock tree for the design with scan chain.
Should I avoid gated clock?
Can anybody help me?
Thanks
Yawei Guo