problems regarding adc of spartan 3e digilent board.

[fool123]

i have problem regrading adc in spartan 3e digilent board. i have made all fsm ,the simulation works well but when i board it didnt work. i have shown the MISO on led 7 and 7 msb adc values in other leds. initiall all leds blinks later all go high irrespective of the input.

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Code VHDL - [expand]
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---------------------------------adc.vhd-------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:48:25 05/05/2013 
-- Design Name: 
-- Module Name:    adc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity adc is
Port (
    clock           : in  STD_LOGIC;                     -- 50 MHz clock from FPGA
     
    rstadc      : in  STD_LOGIC;                     -- reset used to restart the whole ADC process
   ce_amp       : in STD_LOGIC := '0';           -- AMP configuration start, when low amplifier is off
    goconv      : in  STD_LOGIC := '0';          -- ADC starts conversion, when low, adc is off
    ready       : out STD_LOGIC := '0';          -- when conversion is complete ready is set to high    
    SPI_MISO    : in std_logic;                --serial bus used by adc to send data to fpga
    ACONV       : out  STD_LOGIC :='0';        -- to adc, active high shutdown
    ADC0            : out std_logic_vector(13 downto 0) := (others => '0'); -- output port of ADC to send 14 bit data from VINA
    ADC1            : out std_logic_vector(13 downto 0) := (others => '0'); --output port of ADC to send 14 bit data from VINB        
  
 -- AMP in/out signal
    AMP_CS      : out  STD_LOGIC;                    -- AMP chip select     
    MOSI            : out  STD_LOGIC;                -- SPI bus used to send data to programmable amplifier
    SCK             : out  STD_LOGIC                     -- Clock to amp and adc    
    ); 
 end adc;
 
architecture Behavioral of adc is
 
   constant gain            : std_logic_vector(7 downto 0) := "00010001";       -- constant gain of -1 is set for pre amp
    type state_type is (IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD); --different states used for the finite state machine to control ADC and AMP data transfer, the states are based on the codes of Alessandro Giulianelli
   signal next_state, state : state_type;                            
    signal counter      : integer range 0 to 35 :=0;                    --constant defined to monitor the data transfer
                                           --clock used by ADC and AMP
    signal amp_bit_count : integer range 0 to 15 := 0;             -- constant used to monitor 8 bit data transfer to AMP
    signal count            :integer range 0 to 500;                      --Constant used to divide the 50 MHz clock 
    signal temp             :std_logic:='0';                                    --constant used to hold clk value for divided clock
    signal cl: std_logic;
    --signal core_c:std_logic;
 
begin
process(clock,temp)                                      --process is driven by clk and temp
    begin
    if(clock'event and clock ='1') then            -- clk'event makes sure that clk value has changed and clk='1' makes sure that is high
        if(count >=25 ) then                         --count should be<250 for ADC to work i.e.minimum frequency can be reduced
            temp<=not temp;
            count<=0;
        else
            count<= count+1;
        end if;
    end if;
    cl <= temp;
 
end process;
 
 
 
process(ce_amp,goconv,state,counter,amp_bit_count) is --this process is used to change the state to next state, it helps to reduce the time required to change the states in the main process
 
begin
     
         case state is  
            when IDLE =>
            if ce_amp = '1'   then                              -- when ce_amp is 0 amp is set to idle state
               next_state <= START;
                else
                    next_state <= IDLE; 
                end if;
                
            when START =>                                    
                next_state <= START2;   
            when START2 =>
                next_state <= HI;                   
            when HI =>                                           -- high is set to stay for 2cycle that is 2*clk speed, as for amp 50 ns is the minimum clock high time
                if counter = 2 then
                    next_state <= HI_DUMMY;
                else
                    next_state <= HI;
                end if;         
 
            when HI_DUMMY =>                
                next_state <= LO;
            when LO =>                                    -- low is also required to stay for 50 ns
                if counter = 2 then
                    next_state <= LO_DUMMY;
                else
                    next_state <= LO;
                end if;     
            when LO_DUMMY =>
                if amp_bit_count=8 then                    -- 8 bit data from fpga sets the gain of the amplifier
                    next_state <= FINE;             
                else
                    next_state <= HI;       
                end if;
            when FINE =>            
                next_state <= IDLE_AD;                     --sampling starts from here
 
            when IDLE_AD =>                                         
                if goconv ='1' then                               --sampling is controlled by goconv signal
                    next_state <= START_AD;                                                         
                else
                    next_state <= IDLE_AD;
                end if;             
            when START_AD =>                               --unlike amp, adc can work at the speed of 50 MHz so doesn't require extra high time
                next_state <= HI_AD;                    
            when HI_AD =>       
                next_state <= LO_AD;
            when LO_AD =>
                if counter = 34 then
                    next_state <= FINE_AD;
                else
                    next_state <= HI_AD;
                end if;
            when FINE_AD =>
                next_state <= IDLE_AD;
            when others =>          
                next_state <= IDLE_AD;    
        end case;
 
end process;
 
 
process (cl,rstadc) is                       --this is the main process where the digital data is taken from ADC
variable index1 : integer range 0 to 15;        --index1 is used to take data from VINA
variable index2 : integer range 0 to 15;        --index2 is used to take data from VINB
 
begin 
 
if rstadc = '1' then                            --rstadc is used to reset ADC
    state <= IDLE;
elsif cl'event and cl ='1' then
    -- global assign
    state <= next_state;
    ready <= '0';                                           -- busy, setup AMP, acquiring by ADC
    
    case state is 
        when IDLE =>
            SCK <= '0';
            AMP_CS <= '1';
            MOSI <='0';
            counter <=0;
 
        when START =>
           AMP_CS <= '0';
            amp_bit_count <=  0;
            index1 := 7;                                    -- 8 bit value
        
        when START2 =>
           MOSI <= gain(index1);                        -- first assign, and data is sent on LO_DUMMY   
                
        when HI =>
            SCK <= '1';     
            counter <= counter +1;
 
        when HI_DUMMY =>    
            amp_bit_count <= amp_bit_count + 1;
            counter <=0;
 
        when LO =>
           SCK <= '0';              
            counter <= counter + 1;             
                
                if counter = 1 then
                    if index1 > 0 then
                        index1 := index1-1;
                    end if;
                end if;
                
        when LO_DUMMY =>    
           MOSI <= gain(index1);
            counter <=0;                        
            
        when FINE =>
           AMP_CS <='1';
            SCK <= '0';
            MOSI <= '0';    
            
        when IDLE_AD =>
         ready <= '0';                    -- setup AMP complete, waiting goconv enable
            SCK <= '0';
            ACONV <= '0';
            
 
        when START_AD =>
            SCK <= '0';
            ACONV <= '1';
            counter <= 0;
          index1 := 13; -- 14 bit value
            index2 := 13; -- 14 bit value
        
        when HI_AD =>
        SCK <= '1';
            ACONV <= '0';
            counter <= counter +1;
                
        when LO_AD =>
            SCK <= '0';
            ACONV <= '0';
        
                if(counter >2 and counter < 17) then                
                        if index1 = 13 then
                            ADC0(index1)  <= not SPI_MISO;       --here the simple inversion of the 14th bit makes the 2's complement form of the ADC to 14 bit unsigne form, it's just a beautiful conversion step
                        else
                            ADC0(index1)  <= SPI_MISO;           --ADC0 is used to send the unsigne data of channgel VINA
                        end if;     
                        if index1 > 0 then
                            index1 := index1 -1;
                        end if;
                elsif(counter > 18 and counter < 33) then
                        if index2 = 13 then
                            ADC1(index2)  <= not SPI_MISO;
                        else
                            ADC1(index2)  <= SPI_MISO;
                        end if;
                        if index2 > 0 then 
                            index2 := index2 -1;
                        end if;
                else
                    null;
 
                end if;
        
        when FINE_AD =>
              counter <= 0;
                SCK <= '0';
                ACONV <= '0';   
                ready<='1';
                
        when others =>
              SCK <= '0';
                ACONV <= '0';
                AMP_CS <= '1';
                MOSI <='0';
                amp_bit_count <= 0;
 
    end case;
end if;
 
end process;
end Behavioral;
 
 
 
---------------------------------------------main.vhd-------------------------------------
-- Company: 
-- Engineer: DEEPESH LEKHAK
-- 
-- Create Date:    23:55:39 05/05/2013 
-- Design Name: 
-- Module Name:    main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity main is
        PORT( CLK                   : in  STD_LOGIC;   --50 Mhz clock 
              reset1                    :in std_logic;
              LED                   : out std_logic_vector(7 downto 0); --output port for the led
              SPI_SS_B              : out  STD_LOGIC;       -- Serial Flash
           AMP_CS               : out  STD_LOGIC;       -- Amplifier for ADC
           AD_CONV              : out  STD_LOGIC;       -- ADC Conversion start
               
              SPI_MISO              : in std_logic;      -- master in slave out  used to receive data from ADC
              SPI_MOSI              : out STD_LOGIC;     --master out slave in used to send date to AMP and DAC
           SPI_SCK              : out STD_LOGIC;     --clock for amp, ADC and DAC
              FPGA_INIT_B           : out  STD_LOGIC);  -- Platform Flash
end main;
 
architecture Behavioral of main is
 
 
type state_type is (IDLE, READ_ADC, FUNC );
signal state       : state_type:=IDLE;                                    --initial state is idle
signal ADC0         : std_logic_vector(13 downto 0) := (others => '0');    --ADC0 take 14 bit unsigned digital data of VINA
signal ADC1         : std_logic_vector(13 downto 0) := (others => '0');    -- ADC1 take 14 bit unsigned digital data of VINB
signal  ready,goconv,ce_amp ,SCK,MOSI: std_logic;   --these signals are used to control the adc,dac components 
signal pattern      : std_logic_vector(11 downto 0):=(others=>'0');        --this is the signal used to send 12 bit unsigned data to DAC component
                         -- this is used to give the address from where DAC will give its analog output
signal reset        :  STD_LOGIC;    --reset high will take the system to idle state
signal RST          :  STD_LOGIC;    --Reset for DAC
signal rstadc      : STD_LOGIC;     --reser for adc
signal temp : std_logic_vector(13 downto 0) :=(others=>'0');  --this signal is used to hold the temporary data
signal clk0: std_logic;
signal clock: std_logic;
 component adc                                             --adc component declaration
    Port (
    clock       : in  STD_LOGIC;
     
    rstadc  : in  STD_LOGIC;
    ce_amp  : in STD_LOGIC;
    goconv  : in  STD_LOGIC; 
    ready   : out STD_LOGIC := '0';
    SPI_MISO : in std_logic;
    ACONV   : out  STD_LOGIC :='0';
    ADC0        : out std_logic_vector(13 downto 0) := (others => '0');  
    ADC1        : out std_logic_vector(13 downto 0) := (others => '0');           
    AMP_CS  : out  STD_LOGIC;
   MOSI         : out  STD_LOGIC;     
    SCK         : out  STD_LOGIC
  ); 
  
end component;
COMPONENT core_c
    PORT(
        CLKIN_IN : IN std_logic;
        RST_IN : IN std_logic;          
        CLKFX_OUT : OUT std_logic;
        CLKIN_IBUFG_OUT : OUT std_logic;
        CLK0_OUT : OUT std_logic;
        LOCKED_OUT : OUT std_logic
        );
    END COMPONENT;       
 
 
begin
      SPI_SS_B      <='1';        --this is used to disable the unrequired devices so that the bus conflict doesn't arise                     
        --SF_CE0        <='1';
      FPGA_INIT_B   <='1';
          
        reset<='0';
        rstadc<='0';
     
 
 
A1: adc
   Port map (  clock        =>Clock,
                     
                    rstadc  => rstadc,
                        ce_amp  => ce_amp, 
                    goconv  =>goconv, 
                    ready       =>ready, 
                    SPI_MISO    =>SPI_MISO,
                    ACONV   =>AD_CONV,
                    ADC0        =>ADC0, 
                    ADC1        =>ADC1,
                    AMP_CS  =>AMP_CS, 
                    MOSI        =>MOSI,
                    SCK     =>SCK
                  );
     
Inst_core_c: core_c PORT MAP(
        CLKIN_IN => CLK,
        RST_IN => rstadc,
        CLKFX_OUT =>clock ,
        CLKIN_IBUFG_OUT =>open ,
        CLK0_OUT =>clk0,
        LOCKED_OUT => open
    );
 
      
process(clk0,reset1) is               
 
begin
     
    if reset1 = '1' then
        state <= IDLE;
    elsif CLK0'event and CLK0 ='1' then
        
       case state is
         
            when IDLE =>
                 
                    ce_amp <= '1';
                    goconv<='1';
                     led(7 downto 0)<=(others=>'0');
                        state <= READ_ADC;
                 
                    
            when READ_ADC =>    
                 if ready='1' then
                    ce_amp<='0';
                    goconv<='0';
                    state<=FUNC ;
                  else
                  
                    state<=READ_ADC;
                  end if; 
                        
            when FUNC   =>
                temp<=ADC1;
                 
                pattern<=temp(13 downto 2);
                 led(6 downto 0)<=pattern(11 downto 5);
                 led(7)<=SPI_MISO;
                  goconv<='1';
                  state<=READ_ADC;                      
                    
            when others =>          
              state<=IDLE;  
        end case;
    end if; 
end process;
 
process( SCK,MOSI,state) is  -- this process  acts as a resolution function as the ADC, AMP and DAC use the same MOSI and MISO so conflict arises when resolution function is not made
 
        begin   
             if (state=READ_ADC) then
                    SPI_MOSI<=MOSI;
                    SPI_SCK<=SCK;
                
                 else
                  SPI_MOSI<='0';
                  SPI_SCK<='0';
                 end if;
end process;    
 
 
end Behavioral;

---

 

[TrickyDicky]

One this that wont help is your own generated clk, cl. Use cl as a clock enable in the clock domain, not as a clock itself.

 

[fool123]

One this that wont help is your own generated clk, cl. Use cl as a clock enable in the clock domain, not as a clock itself.

THANX for your reply. I also tried without using generated clock but output is same.

- - - Updated - - -

One this that wont help is your own generated clk, cl. Use cl as a clock enable in the clock domain, not as a clock itself.

THANX for your reply. I also tried without using generated clock but output is same.