Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problems of post-layout simulation using Calibre LVS/PEX

Status
Not open for further replies.

ccarrot

Newbie level 6
Newbie level 6
Joined
Sep 19, 2007
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,399
Hi all:

I'm facing a problem about the Calibre LVS/PEX, I will describe it using this simple current mirror shown below, X and Y are same MOSFETs with width=16, nfing=2, m=1:

1.png

When I just do the layout with only one finger for both X and Y (w=16, nfing=1, m=1), and do the post-layout simulation, I injected 100uA to node Vb, it has no problem seen from the post-layout schematic: X will absorb 100uA and Y will source 100uA.

But when I use 2 fingers, the problem comes. The layout is:

2.png

In this layout, the X and Y are in a single transistor which has w=32 and nfing=4, that means, X/Y are w=16, nfing=2 which is the same with the schematic above. ------ This is in my mind what is correct.

But when we do the LVS, it failed and showed property errors that X/Y has 2 fingers in the schematic but has 4 fingers in the layout:


3.png



If change some MOS properties in the schematic, nfing is changed from 2 to 4 (layout doesn't change), then hen the LVS passes, which we think is not correct (but it passes!). I used this extracted CalibreView file to do the post-layout simulation, the current reduced to a half as seen the comparison below:


Pre-simulation, both X and Y have 100uA current:

7.png

Post-simulation, the current reduced to only 50uA:

8.png




Does anybody know what would be the problem is and give some help? Thank you SO MUCH for any suggestions cuz I've been on this problem for days. Thank you!
 

Hi all:

I'm facing a problem about the Calibre LVS/PEX, I will describe it using this simple current mirror shown below, X and Y are same MOSFETs with width=16, nfing=2, m=1:

View attachment 101041

When I just do the layout with only one finger for both X and Y (w=16, nfing=1, m=1), and do the post-layout simulation, I injected 100uA to node Vb, it has no problem seen from the post-layout schematic: X will absorb 100uA and Y will source 100uA.

But when I use 2 fingers, the problem comes. The layout is:

View attachment 101042

In this layout, the X and Y are in a single transistor which has w=32 and nfing=4, that means, X/Y are w=16, nfing=2 which is the same with the schematic above. ------ This is in my mind what is correct.

But when we do the LVS, it failed and showed property errors that X/Y has 2 fingers in the schematic but has 4 fingers in the layout:


View attachment 101043



If change some MOS properties in the schematic, nfing is changed from 2 to 4 (layout doesn't change), then hen the LVS passes, which we think is not correct (but it passes!). I used this extracted CalibreView file to do the post-layout simulation, the current reduced to a half as seen the comparison below:


Pre-simulation, both X and Y have 100uA current:

View attachment 101044

Post-simulation, the current reduced to only 50uA:

View attachment 101045




Does anybody know what would be the problem is and give some help? Thank you SO MUCH for any suggestions cuz I've been on this problem for days. Thank you!


Anyone can help? Here is some more information of the netlist:


The netlist of the schematic is:
==============================
==========
.SUBCKT test A GND Vb

*.PININFO A:B GND:B Vb:B

MM1 Vb Vb GND GND nsvtlp_rf w=16.0 l=0.5 nfing=2 srcefirst=0 ngcon=2 m=1
+ mult=1 ncrsd=1

MM2 A Vb GND GND nsvtlp_rf w=16.0 l=0.5 nfing=2 srcefirst=0 ngcon=2 m=1 mult=1
+ ncrsd=1

.ENDS
========================================


and the netlist of the extracted layout (only for the MOSFETs):
=========================================
.SUBCKT test Vb GND A

** N=259 EP=3 IP=0 FDC=4

M0 Vb Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=17420 $Y=-12305 $D=262
M1 A Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=18120 $Y=-12305 $D=262
M2 A Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=18820 $Y=-12305 $D=262
M3 Vb Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=19520 $Y=-12305 $D=262
.ENDS

=========================================


It looks like the tool only considers one single MOSFET in the layout. In our LVS rules file, we have set:

LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS NO
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES NO
LVS REDUCE PARALLEL BIPOLAR NO
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS NO
LVS REDUCE SERIES RESISTORS NO
LVS REDUCE PARALLEL RESISTORS NO
LVS REDUCE PARALLEL DIODES NO

But the error is still there.

Thanks in advance!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top