Problems in using for loops in verilog RTL

[dll_fpga]

For RTL coding of hardware's such as decoder we can use case statement as well as for loops..
But if we use for loops the code size will be less..

Any problem in using for loops?(in hardware replication circuits like this?)

will synthesis /linting tools support?(synopsis /cadence/attrenta)

 

[sakthikumaran87]

Re: For loop in verilog RTL

For loops are very well synthesizable and can be used in coding for ASIC. But in general, coding with For loops are not generally prescribed. I am not very confident with the reason why it is not prescribed. Might be it is because of the fact that when for loop is utilised then the loop will be the bottle neck for the max. frequency of the design.

 

[dll_fpga]

Re: For loop in verilog RTL

For loops are very well synthesizable and can be used in coding for ASIC. But in general, coding with For loops are not generally prescribed. I am not very confident with the reason why it is not prescribed. Might be it is because of the fact that when for loop is utilised then the loop will be the bottle neck for the max. frequency of the design.

if the design itself require hardware replication ...like the case of a decoder...is it ok to use for loop?