I was under the assumption that you simulated the master with a slave model, which would be the preferred procedure. Thus my question about SDA pull-up. It would be generated in the test bench by a weak high driver for SDA. If SCL uses open drain as suggested by the I2C standard, it needs a pull-up too.
If no slave is utilizing clock stretching, SCL can be driven push-pull in a simplified master. SDA should however use open drain driver, apparently not implemented in your code.
Before spending the effort to code an I2C slave model, or search it on the internet, you could compare the timing of the master simulation against I2C specification. At first sight, you are missing to generate a correct start sequence, a sufficient condition for master failure.