problems in semi-custom design

[zubairbasha]

hello every1,

i am a begineer learning cadence tool, i am 1/4th way down the journey , i have learnt fullcustom and semi-custom design at basic level .... can any one tell me how to abtain a schemetic in virtuoso for a gate-level-netlist generated after synthesis (meeting all constraints).. i have used "RTL- COMPLIER" for synthesis and "nc-launch" for verilog coding..........


and can any one guide me how to learn advanced STA concepts and optimization techniques (material )

Thanks in advance
zubair.