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PROBLEMs clock gating in FPGAs

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aureage

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hello everyone
when i use FPGA to do verification about ASIC's gated clock, this issues (clock gating) occurred , i use synplify_perimer_dp to synthesis ,

when i set "Fix Gated Clocks" as '0' the geted cell logic was existed exactly , but when i set "Fix Gated Clocks" as '3'
my geted cell module was removed,by waring:

"Removing sequential instance X of view:X because there are no references to its outputs "

I have checked all outputs from the module ,all of them are connected correctly

somebody help me ,thans a lot ...
 
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