Jun 20, 2006 #1 E eddsos Junior Member level 2 Joined Mar 22, 2004 Messages 21 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 153 formality problem I have one register in netlist, whose data input enable is always invalid. So, this register should be 0 after reset, which is a redundant logic. How can i let formality know this when compare downstream logics?
formality problem I have one register in netlist, whose data input enable is always invalid. So, this register should be 0 after reset, which is a redundant logic. How can i let formality know this when compare downstream logics?
Jun 21, 2006 #2 H hawk_chenbo Member level 2 Joined Sep 28, 2004 Messages 43 Helped 3 Reputation 6 Reaction score 1 Trophy points 1,288 Activity points 254 formality constant I wonder why you don't remove this redundant register.
Jun 21, 2006 #3 J jackson_peng Full Member level 2 Joined Apr 11, 2005 Messages 139 Helped 24 Reputation 48 Reaction score 9 Trophy points 1,298 Location Shanghai, China Activity points 2,380 just set constant value on the reg out, before you start verify
Jun 22, 2006 #4 S spauls Advanced Member level 2 Joined Dec 17, 2002 Messages 524 Helped 26 Reputation 52 Reaction score 9 Trophy points 1,298 Activity points 3,355 try synthesis again with set_case_analysis , and then do formality your problem will be olved.