Problem with verifault-xl

[eda4you]

Hi!

I got follwing problem:

If I start to simulate using verifault-xl with I got following warnings:

"Warning! Skipping foreign VERIFAULT-XL task: $fs_modell [VERILOG -SFTFN]"
and simulation stopps.

and I don't know why. Otherwise normal simulation works fine as well as using verifault-xl via shell.

Had someone of you the same problem and does someone know how to overcome it?



Thanks anyone for constructive contributions

 

[maxsnail]

Hi,
Verifault used to do what, fault simulation for tester patterns????
can you give me some information

Regards,
Snail

 

[eda4you]

It's generates digital test vector for several faults like stuck at 0, ....


Unfortunately development has been stopped by cadence and I don't know they have a substiute. The new university package has a lot of new tools inthere. Have to take a look at and will report you if u want.

 

[maxsnail]

ok,
I used synopsys TetraMax ATPG to do that,
it is a powerful tools, especial its schematic viewer/debugger