Problem with using components in vhdl

mhmmdrz92 · Jan 25, 2018

I want to use carry look ahead and ripple carry adder components to write a vhdl code of a combinational adder. the inputs are 16 bits an the components are 4 bits, so i would use four of them. this is the code:

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity ETAII is
  port (
    A  : in std_logic_vector(15 downto 0);
    B  : in std_logic_vector(15 downto 0);
     --cin : in std_logic;
    --
     c_out : out std_logic;
    result : out std_logic_vector(15 downto 0)
    );
end ETAII;
 
architecture rtl of ETAII is
 
    component carry_lookahead_adder is
        generic (g_WIDTH : natural := 4);
       port (
         i_add1_cla  : in std_logic_vector(g_WIDTH-1 downto 0);
         i_add2_cla  : in std_logic_vector(g_WIDTH-1 downto 0);
         c_in_cla : in std_logic;
         --
         c_result_cla : out std_logic
         
         );
    end component carry_lookahead_adder;
 
    component ripple_carry_adder is
      generic (g_WIDTH : natural := 4);
      port (
         i_add1_rca  : in std_logic_vector(g_WIDTH-1 downto 0);
         i_add2_rca  : in std_logic_vector(g_WIDTH-1 downto 0);
         c_in_rca : in std_logic:='-';
         --
         o_result   : out std_logic_vector(g_WIDTH-1 downto 0)
         );
    end component ripple_carry_adder;
 
    signal c1,c2,c3,c4 : std_logic;
    signal result1 : std_logic_vector(15 downto 0);
 
begin
 
    cla1: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(3 downto 0),
        i_add2_cla => B(3 downto 0),
        c_in_cla => '0',
        c_result_cla => c1);
 
 
    rca1: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(3 downto 0),
        i_add2_rca => B(3 downto 0),
        c_in_rca => '0',
        o_result => result1(3 downto 0));
 
        
    cla2: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(7 downto 4),
        i_add2_cla => B(7 downto 4),
        c_in_cla => '0',
        c_result_cla => c2); 
 
 
    rca2: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(7 downto 4),
        i_add2_cla => B(7 downto 4),
        c_in_rca => c1,
        o_result => result1 (7 downto 4));
        
    cla3: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(11 downto 8),
        i_add2_rca => B(11 downto 8),
        c_in_cla => '0',
        c_result_cla => c3);
 
 
    rca3: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(11 downto 8),
        i_add2_rca => B(11 downto 8),
        c_in_rca => c2,
        o_result => result1 (11 downto 8));
        
    cla4: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(15 downto 12),
        i_add2_cla => B(15 downto 12),
        c_in_cla => '0',
        c_result_cla => c4);
 
 
    rca4: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(15 downto 12),
        i_add2_rca => B(15 downto 12),
        c_in_rca => c3,
        o_result => result1 (15 downto 12));
    
result <= result1;
c_out <= c4;
 
end rtl;

I recieve these similar errors from altera quartus:

Error (10349): VHDL Association List error at ETAII.vhd(67): formal "i_add1_cla" does not exist
Error (10346): VHDL error at ETAII.vhd(66): formal port or parameter "i_add1_rca" must have actual or default value
Error (10784): HDL error at ETAII.vhd(32): see declaration for object "i_add1_rca"
Error (10346): VHDL error at ETAII.vhd(66): formal port or parameter "i_add2_rca" must have actual or default value
Error (10784): HDL error at ETAII.vhd(33): see declaration for object "i_add2_rca"

What should I do to solve this error?

TrickyDicky · Jan 25, 2018

is this a copy past error?
the ripple_carry_adder port is called i_add1_rca
You have tried to connect to i_add_cla (which doesnt exist on the component).

mhmmdrz92 · Jan 25, 2018

yes, the errors are pasted from the software.
I didn't get your hint about the question and i don,t know how to solve the problem

TrickyDicky · Jan 26, 2018

change this:

Code VHDL - [expand]
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cla3: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(11 downto 8),
        i_add2_rca => B(11 downto 8),
        c_in_cla => '0',
        c_result_cla => c3);

to this:

Code VHDL - [expand]
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3
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cla3: carry_lookahead_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(11 downto 8),
        i_add2_cla => B(11 downto 8),
        c_in_cla => '0',
        c_result_cla => c3);

ads-ee · Jan 26, 2018

That is not the only set of copy paste errors. You should have used a generate.

mjuneja · Jan 26, 2018

I can see some more errors in the lines 66-70.

Code:

        rca2: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_cla => A(7 downto 4),
        i_add2_cla => B(7 downto 4),
        c_in_rca => c1,
        o_result => result1 (7 downto 4));

should be replaced by

Code:

    rca2: ripple_carry_adder generic map (g_WIDTH => 4) port map(
        i_add1_rca => A(7 downto 4),
        i_add2_rca => B(7 downto 4),
        c_in_rca => c1,
        o_result => result1 (7 downto 4));

Problem with using components in vhdl

mhmmdrz92

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TrickyDicky

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mhmmdrz92

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TrickyDicky

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Code VHDL - [expand]
1 2 3 4 5	cla3: carry_lookahead_adder generic map (g_WIDTH => 4) port map( i_add1_rca => A(11 downto 8), i_add2_rca => B(11 downto 8), c_in_cla => '0', c_result_cla => c3);

Problem with using components in vhdl

mhmmdrz92

Newbie level 2

TrickyDicky

Advanced Member level 7

mhmmdrz92

Newbie level 2

TrickyDicky

Advanced Member level 7

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mjuneja

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