Problem with uninitialized signals when running VHDL simulation on ModelSim

[adamsogood]

Hi,

I have issues when I am running VHDL simulation on ModelSim. The problem is that some signals are not initialized properly (because it is a big design, so i can't assign the initial values to each signals). The uninitialized signals may assign 'X' and 'U' values and cause some unexpected simulation results. I am trying to find out which uninitialized signal is the troublemaker. But the ModelSim didn't give much run-time hints.

any idea?
Thanks,

adam

 

[echo47]

initializing signals in vhdl

It's your job as HDL designer to correctly initialize the necessary signals. The size of the design shouldn't affect your ability to initialize the necessary signals. Depending on the design and your simulation goals, some signals may need to be initialized, and others deliberately uninitialized. From the simulator's point of view, initialized signals and uninitialized signals are both acceptable, so it can't really help you with troubleshooting.

 

[kvingle]

modelsim vhdl inout

I agree with the previous post.It's the standard practice to be followed.
but you can know the drivers of a particular signal in wave window by right clicking on its wave.Once you know the all the drivers of your signal under analysis you can initialize them as needed. and simulate the design again to expect proper results.But this is not a good practice.

regards
Kishor.

 

[salma ali bakr]

vhdl data not initialized in waveform modelsim

you have to either initialize them in your design or in the wave form window itself or in your testbench...

 

[amir81]

simulate bidirectional ports modelsim

your design should have some components and you use them in your top module.
first you should be sure that these components are written correctly. define new projects in modelsim and write testbenches to ensure. i think you might make some mistakes in these components.

 

[FvM]

vhdl uninitialized value modelsim

ModelSim actually requires initialization of any internal signal that does not depend on reset or another signal. E. g. if you have a simple frequency dividing counter, in most cases it wouldn't need an initialization in a real hardware design. It could start with an arbitrary value, furthermore it would actually have a well defined power-on reset state in most FPGA families. But ModelSim doesn't know about default power-on states, sets the signal to 'X' and the counter will never give any output unless you set it to a defined value. If an asynchronous reset isn't intended for a particular signal, giving an initial value in signal definition would be enough, e. g. signal count : unsigned(3 downto 0) := (others => '0');.

 

[adamsogood]

modelsim uninitialized value

Hi, folks,

Thank you for all your replies. Actually, the problem results from 'X'/'U' signal assignments, but the 'X'/'U' are not caused by improper initialization. it is all about the bi-directional signals.

I am designing a DDR2 memory controller. In the very top design, there is a port signal called DDR2_DQSp. It is a bidirectional data strobe signal shared by both READs and WRITEs.

This port signal is declared as follows:
DDR2_DQSp : inout std_logic_vector((DQS_WIDTH-1) downto 0);

In the testbench, this port signal is hooked up to the Micron Verilog Simulation Model. Inside the design, it was driven by signals as follows:
DDR2_DQSp <= ddr2_dqs_int;

the signal ddr2_dqs_int is driven by a bidirectional port signal from a sub-component(one hierarchy level below the very top design). After watching the waveform, I found out that DDR2_DQSp becomes 'x'.....

Then, I hooked up DDR2_DQSp directly to the bidirectional port signal in the sub-component, the problem is gone.


In summary, the bidirectional port signals have to be dealt with properly; otherwise, modelsim will drive it to 'X'


Thank you

 

[FvM]

modelsim bidirectional ports

It may be necessary to add an additional initialization to :=(others =>'Z') or it's verilog equivalent for bidirectional ports of submodules. In VHDL, it can be included in the port definition. It's not required for synthesis but for ModelSim.