Problem with understanding PSRR of OTA

[ambreesh]

Hi,

If any of you have read the following paper, please help.

Power supply rejection ratio in operational transconductance amplifiers
Willy Sansen and M S J Steyaert IEEE transaction on circuit and systems Sept 1990

The sign convention is not clear for e.g eq6 and eq7 similarly for eq9 , observe the sign for (go5+scp5) .
I feel that explanation for PSRR for "The source coupled input satge with active load" is not as per the procedure defined in the paper. If I do not understand it could one of you please help.
The paper is already uploaded in Request for IEEE papers forum

 

[paulux]

ota psrr

The signs for eq6,7 should be correct. You can consider like this by modeling M5 to be a passive devices with an equivalent G=go5+sCp5. Then when Vdd increases, more current injects into M8 and then is mirrored by M7 to output node and thus increase iout sinking. By assuming the iout sinking to be positive, you would get eq 6 & 7.
Or you can derive the detailed small signal model of the fig.4 and then set vdd as your ac input and calculate. This is the most complete way to confirm your argument.

 

[ambreesh]

psrr small signal

Hi,
But we have equation7 derived from eq6. And we can expect a printing error.
Also the papers explains a easier method of finding PSRR, so do not want to have a complete small signal model.
Also look into the PSRRvdd explanation for "Source coupledInput stage with active load", try implementing the procediue he has suggested and what explanation is given. I could not correlate the two. If you could help.

 

[paulux]

Re: PSRR OTA

Thanks for your reading.
I totally agree with you that eq7 should be printing error.
The author in that paper just simplifies the analysis by assuming that
(1)the resistance of diode-connected M3 is so small (as compared with go1)that any vdd variation would go into node a.
(2)any voltage variation on the node a would flows to the node vc(source terminals of M1 & M2) through go1. Then the voltage on vc would go completely to node b through the common-gate configuration of M2. Therefore, the "barrier" for the vdd ac signal path passing M3, M1 & M2 is only go1. Similarly another path through M4 to output is just go4. Since go1 & go4 are in parallel, the equivalent G=go1+go4. Similarly apply to capacitor case.

 

[ambreesh]

Re: PSRR OTA

Hi,

This is how I understood, if we go as per the procedure, the current transfre function is from M3 M4 current mirror to the gain node. The current that is to be applied to the cutside that has the current transfer function, must flow from vdd to that cut side. This would lead to M4 sourcing current t the gain node.

Do we concider that Vc node potential vary as go1.vdd current flows into it. Which leads to variation in source potential of M1 nd M2 the differential pair and gmVgs current flows through sources of M1 nd M2.
If we concider the current flowing from M1, this flows from Drain to source for M3 and M3 would mirror it in the same way into M4 and in a way sinking that current from gain node. But the current going from M2 to gain node would be entering into gain node and as both the magnitude of currents are same but opposite direction they cancel.
I am not sure of this thought but it would be nice if you could shed some light on it

 

[paulux]

Re: PSRR OTA

Hi ambreesh,
Your arguments are logical & reasonable. But I guess that the author approximated the M3 as a very very small equivalent resistor that very small amount of "ac" voltage difference between Vdd & node b is generated. This very small ac voltage is insufficient to cause M5 to mirror the ac current.

In my opinion, the above are just approximation that could be justified if all values of gm, ro & C are available for approximation.
Please kindly comment or give some opinions on my views above.