Problem with uart transmitter code vhdl

[dejwid30]

Hello
I'm writting a code for a transmitter and I don't know what I do wrong in my code or what I must add to my code?

Thank You for help

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity transmitter is
port(

CLK_50MHz : in std_logic;
--rx : in std_logic;
tx : out STD_LOGIC--_VECTOR(8 downto 0)
);
end transmitter;

architecture Behavioral of transmitter is
type fsm_state1 is (IDLE,DATA,STOP);
signal state_id1: fsm_state1 := IDLE;
--------------------------------------------- Transmitter signals


signal enable : std_logic:= '0';
signal transmit : std_logic;
signal transmit_enable : std_logic;
signal data_tx : std_logic_vector(7 downto 0); --:="01100001";
begin
Tra: process (CLK_50MHz)
variable count1 : natural range 0 to 7 := 0;
begin

if(CLK_50MHz'event and CLK_50MHz = '1') then

case state_id1 is

when IDLE =>


if (enable ='1') then
if (transmit = '1') then
transmit_enable <= '1';
state_id1 <= DATA;
end if;
end if;
transmit <= '0';



when DATA =>
if(transmit_enable = '1') then
if(count1 < 7) then
tx<=data_tx(count1);
count1:=count1+1;
transmit_enable<='1';
if (count1=7) then
transmit_enable<='1';
else
count1 :=0;
state_id1 <=STOP;
end if;
end if;
end if;

when STOP =>
transmit_enable <='0';
state_id1 <=IDLE;



when others =>
state_id1 <= IDLE;

end case;
end if;
end process;
DIV: process (CLK_50MHz)
variable cnt : natural range 1 to 2604 := 1;
begin
if rising_edge(CLK_50MHz) then

if cnt >= 2604 then
cnt := 1;
enable <= '1';
else
cnt := cnt + 1;
enable <= '0';
end if;

else
enable <='0';
end if;

end process DIV;

 

[barry]

what is your problem? what are the symptoms? what is your input? what is your output?