Problem with timing and multiple edges in Manchester Encoder circuit

[Msakhy]

I'm trying to design a Manchester Encoder circuit using a PISO shift register and an XOR gate. I ran into a couple problems.

1. Timing: I need to synchronize the shift register output with the clock (clocking it) i.e. I need to delay the clock (running at 100 kHz) by td (the IC’s time delay) which about 16ns.

2. Multiple edges: I need to eliminate the edges caused by the simultaneous switching of logic states of the gate (XOR) inputs (i.e. NRZ/binary data and clock signal respectively)

Help in this regard would be highly appreciated. An alternative design is also welcome!!!

Email me at: khumalosn@webmail.co.za

 

[Jepeto]

Re: Manchester Encoder

Play with this some years ago
Don’t remember what and way I done
All gates are 10ns pd

 

[Msakhy]

Re: Manchester Encoder

I tried to simulate your circuit and I come across problem 2 mentioned above. I want to know if you actually built the circuit. If so, what SIPO shift register IC did you use (I used a 4015 in my simulation) and at what frequency were you clocking the system. I also have trouble tracing how the data generator works.

 

[Jepeto]

Re: Manchester Encoder

NO, its only simulation and the shift register is virtual
The data generator is liner feedback shift register all components have 10n pd the clock frequency 100Khz

 

[PaulHolland]

Re: Manchester Encoder

Hi, Its very simple. Use a D_FF (D flip flop) and an XOR. The Q output of the D-FF is going to one input of the XOR and the other XOR input is going to the input of the D_FF. Now you put you data stream into the D-FF and use the clock to clock the D-FF. this is how you make perfect MCH.

Paul.

 

[Jepeto]

Re: Manchester Encoder

Hi PaulHolland,
Yes, XOR its good idea

 

[PaulHolland]

Re: Manchester Encoder

Hi, Your almost correct. I used a simple D_FF and an XOR function. Decoding can be done with a simple D_FF, in the clock input you put the clock signal and D will be MCH coded signal. That is all .

Paul.

 

[Msakhy]

Re: Manchester Encoder

Hi

The problem is that in real life , the transition of logic state is delayed i.e. a ramp function (with rise time = tr and fall time = tf). When the inputs of the XOR change state at the same there are undesired edges (spikes) at the output. SEE PROBLEM TWO ABOVE. Most simulators will actually show this phenomenon – I see your timing diagrams do not show this. The D-FF method exhibits the same results, (i.e. “confused” XOR at simultaneous transitions) I simulated it on EWB Multisim9. Yes the cascaded and gates do solve the delay problem (PROBLEM ONE ABOVE).

 

[Jepeto]

Re: Manchester Encoder

I think spikes occur because the clock not synchronize with the shift register output
To avoid glitch try to use double frequency clock
Clock/2 used for the shift register and clock used for sampling DFF
Because clock previous to clock/2 DFF will latch data before spike occur by clock/2
The output will delayed by 1 Clock/2 cycle



Schematic error CLK/2 should be connect to Q and not to QN