problem with the output

[QMA]

Dear all
I have calculated the value of out in verilog using xilinx vertex 6. it has to generate a message 'Data Validated' if out == 1 else 'Data Not Validated'. whenever i run the testbench, it gives me three times 'Data Not Validated' and one time 'Data Validated' provided out ==1. For out==0 it gives me 'Data Not Validated' four times. How can I control the output and get only one time 'Data Validated' for out ==1 else 'Data Not Validated'. i have designed following code

if(out==1)
			begin
			$display("Data Validated");
		   if(R_addr==0)
			table_index = pop_count - 1'b1;
			else
			table_index = count + pop_count;
		   if(R_addr==0)
			table_index = pop_count - 1'b1;
			else
			table_index = count + pop_count;
			end
			else
					if(out==0); 
			begin
			$display("Data nnnot Validated");
			end

 

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The code above will display "Data Validated" once every time the if (out==1) is evaluated. It will also display "Data nnnot Validated" every time this block of code is evaluated as you have a semicolon at the end of if(out==0);. Perhaps that is a typo? If the semicolon was unintentional then the second $display will occur once each time the if(out==1)...else if(out==0) if statement gets evaluated.

Your problem with repeated $display calls is NOT in this part of the code. Why does everyone think they know what part of their code is broken and NEVER show the entire code in context?

You should use CUT & PASTE of your original file to add code to your thread, not typing it in by hand, so you don't end up with code that is functionally incorrect.