Problem with synthesizing DCM module

[mindstream]

im using xc3s400 (Spartan 3) FPGA for my project i needed to use frequency synthesizer inside the
DCM module.
I simulated my Verilog code and tried synthesizing it but the DCM primitive itself was found to be non synthesizable:!: (It makes use of some time variables which are non synthesizable ).

What can i do to fix the problem:?:

 

[aafaq]

Re: DCM synthesis

refer this document


Added after 5 minutes:

more over u can try this
Here's a Verilog example that generates 44100 Hz from 50 MHz using two DCM frequency synthesizers and a counter:

#738182

 

[echo47]

DCM synthesis

Hi mindstream, Which synthesis software are you using?

If you show us your code and the full error message, someone here can probably help you figure out what's going wrong.