Simulating PAR model
Why are you trying to simulate the PAR model? Are you having problems with the actual design?
Typically, we never attempt to simulate the PAR model. Instead, we do functional simulation on the HDL code itself and then rely on timing constraints to insure the FPGA will run at speed. (We do not simulate PAR models, because they run too slow and take too much effort to get working.)
If you have not done functional simulation, I would start with that. In Xilinx designs, we have to include "glbl.v" to get the designs to come out of reset. We also need to include several of the Xilinx simulation libraries like the unisim and simprim libraries. Get functional simulation working first before tackling simulating PAR models.
Post back exactly what the state of the signals are: They they stuck at high -Z, at '1' or '0' or at unknown, aka 'X'.