[SOLVED] Problem with simple binary counter

[gmish27]

I am stuck at a problem that is taking lot of time for me to solve out. I wanna make a simple binary counter of 'n' digits. Now the code that has been provided in the book is given below to implement the same:

//code from book:

module sc #(parameter n=2)(
input clk,
input reset,
output [n-1:0] signal
);

wire [n-1:0] r_nxt;
reg [n-1:0] r_reg;

always@(posedge clk,posedge reset)
if(reset)
r_reg <= 0; //{n{1'b0}}
else
r_reg <= r_nxt;

assign r_nxt = r_reg + 1;
assign signal = r_reg;

endmodule

Well i did not follow it and wrote my own as below:

//my own code for the same problem:

module sc #(parameter n=2)(
input clk,
input reset,
output reg [n-1:0] signal
);

always@(posedge clk,posedge reset)
if(reset)
signal <= 0;
else
signal <= signal + 1;

endmodule

Firstly if anyone finds an error in my code, or any difference in the above two codes, then please tell me about it.

Secondly, I myself did not find any difference as with Xilinx simulator I am getting the same output for both of the codes. The corresponding Testbench file is given below:

//Generated testbench as HDL, the same used for both the codes

`timescale 1ns/1ps

module sctbw;
reg clk = 1'b0;
reg reset = 1'b0;
wire [1:0] signal;

parameter PERIOD = 200;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 100;

initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end

sc UUT (
.clk(clk),
.reset(reset),
.signal(signal));

initial begin
// ------------- Current Time: 385ns
#385;
reset = 1'b1;
// -------------------------------------
// ------------- Current Time: 585ns
#200;
reset = 1'b0;
// -------------------------------------
// ------------- Current Time: 1385ns
#800;
reset = 1'b1;
// -------------------------------------
// ------------- Current Time: 1585ns
#200;
reset = 1'b0;
// -------------------------------------
// ------------- Current Time: 2385ns
#800;
reset = 1'b1;
// -------------------------------------
// ------------- Current Time: 2585ns
#200;
reset = 1'b0;
// -------------------------------------
// ------------- Current Time: 3385ns
#800;
reset = 1'b1;
// -------------------------------------
// ------------- Current Time: 3585ns
#200;
reset = 1'b0;
// -------------------------------------
// ------------- Current Time: 4385ns
#800;
reset = 1'b1;
// -------------------------------------
// ------------- Current Time: 4585ns
#200;
reset = 1'b0;
// -------------------------------------
end

endmodule

Thirdly, the main problem, at a reset trigger I expect a zero output from the signal line for just one clock cyle.

For the first reset trigger at 385ns the ouput stands on my expectations but scenario changes with the other triggers. At simulation timings of 4385ns, 3385ns, 2385ns, 1385ns I am getting a zero output signal for two clock cyles!!!

So please tell me the mistake and how to correct it cos i want a zero signal ( a restart) for just one clock cycle.

 

[dcreddy1980]

There is no problem with the code.

Its the testbench which causes your o/p to stay at "0" for two clock cycles. The counter has wrapped to "0" before you have applied the new reset and that causes the o/p to stay for two clock cycles.

Make the below change for reset trigger :
// ------------- Current Time: 1385ns
#1000;

 

[gmish27]

Oh ho, such a silly mistake and i did not notice. Was searching for the reason of the fault deliberately. Thankyou sir for ur help