Problem with signal state_reg in simple traffic light controller

[tarang]

hey guys i hope u can help me out... i want to design a simple traffic
light controller according to the 4 states shown in the code below. my
only problem is that my signal state_reg is not changing form one
state to another. this is because the counter i included in the the
code as a process is not working. green to yellow time wait is 30 sec
and yellow to red is 5 sec. my clock period will be 5 sec. so can
anyone help me out

----------------------------------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rbut std_logic
);
end TLC;

architecture Behavioral of TLC is

type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic;

begin

-- behavior describe the counter
process(clk, count, clear)
begin
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
Q <= Pre_Q;
end process;


-- state register


process(clk,reset)
begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;

-- next state logic

process(state_reg,Q,sa,sb)
begin

case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;

when b =>

if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;

when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;

end if;
end if;

when d =>

if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;

process (state_reg)
begin
Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';

case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';

when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';

when d =>
Gb <= '0';
Yb <= '1';

end case;

end process;

end Behavioral;

Added after 1 hours 4 minutes:

i think above code will take your time...so just tell me how can i implement a counter in my simple traffic light VHDL code. it has 4 states. {(Ga,Rb), (Ya,Rb), (Ra, Gb), (Ra, Yb)}

Green to yellow = 30 sec
Yellow to red = 5 sec

thanx

 

[piopix]

Re: Simple traffic light

You shall clear variable count=0 i set clear=1 and Pre_Q = "0000" in reset='0'.
You program is just below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rbut std_logic
);
end TLC;

architecture Behavioral of TLC is

type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic:='0';

begin

-- behavior describe the counter
process(clk, count, clear, reset)
begin
if(reset='0') then
Pre_Q <= "0000";
Q <= "0000";
else
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end if;
Q <= Pre_Q;
end process;


-- state register

process(clk,reset) begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;

-- next state logic
process(state_reg,Q,sa,sb,reset) begin

if(reset='0') then
count <= '0';
clear <= '1';
end if;

case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
count <= '0';
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;

when b =>
if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;

when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;
end if;
end if;

when d =>
if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;

process (state_reg) begin

Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';

case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';
when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';

when d =>
Gb <= '0';
Yb <= '1';

end case;
end process;

end Behavioral;

Remember that you must clear and set used signal in suitable process.

Piopix

 

[salma ali bakr]

Re: Simple traffic light

why did you put "count" in the sensitivity list of the counter...doesn't it only function when the clock edge is rising (not needed in list, since it has to wait for clock edge anyway)...

where is the "else" of the "if (count = '1')"...

and as stated above, make sure you initialize all signals...

 

[tarang]

Re: Simple traffic light

Hey thanx for the Solution...now it works...cool!!

 

[anushina]

Simple traffic light

Hey, it's been a while since you've done this project but hope you still remember the details...
What kind of board did you use to implement the traffic light and what kind of software?
I'm currently working on the same Lab and need some help. I have Spartan 3 XSA-3s1000 board and using Xilinx ISE Webpack 10.1...
Thanks
Ganna