hi and thanks for your attention
some information about problem is here.
first core is a simulation of a standard.it occupies only 30k of fpga capacity, but uses 90% of selected block ram of virtex e.it was run(simulation and implement) successfully on virtex e.
second core is a pci core(it is interesting that a unknwon company can write this core very cheap,comparable with xillinx,...)
this core uses a interface program .data input to pci core,than interface convert it to compatible data for standard input.
this core is run without error on virtex e too.(of cource for shortage of selected block ram it wors on 16 bits mode).
now ,when i run this two program erros accure and output of first core become XXXXX. i couldn't run these two cores thoghether.
i hope thin notes are usefull.
king regards
baa110