Problem with Running Assura LVS on standard Cell Library

[nasroulm]

Hello,

I am using TSMC0.25Lo[Logic] to make an ASIC chip using the standard cell libraries. After synthesis and importing into the cadence I am trying to run LVS on my design.
The problem I am running into is the cells are front end view so I can't see the guts of them and I want to tell Assura to stop at cell level when extracting the netlist from layout and layout.

Has any one have any idea, how to do that?

Thank you

Mo

 

[erikl]

With Diva - an ancestor of Assura - we used to change the stop view in the stop lists:

schematic view stop list: "symbol" "schematic" "cmos_sch" "cmos.sch"
layout view stop list: "abstract" "layout"

Don't know if this method still works with Assura.

 

[nasroulm]

Thank you So much for the hint.
Would you be more specific on where I can find the where I can find the layout view stop list?
I was able to see the schematic view stop list by clicking on the Netlisting Options.

 

[erikl]

Would you be more specific on where I can find the where I can find the layout view stop list?

I don't have access to Assura currently, so I can't tell you exactly, sorry. May be it isn't even necessary to change the layout stop list, as the extraction would stop automatically at the abstract, because it can't go deeper anyway. Or may be you can change this in the Assura LVS setUp by clicking the Netlist Options... button (top right) :

If you run Assura interactively (from the Unix/Linux command line), see the files in the assuraVerification directory below. Read the README file for usage. The assuraLVS.dsf file contains an avStopList, with which you could stop the extraction at abstract (or whatever your "bottom" view is named).

Good luck!

 

[nasroulm]

I just realize that I was not specifying the rsf file, after doing so I am getting an error in regard to :
ERROR The fifth parameter must specify the substrate pin or nil in the mosDevice command.

I attached figures of my setting. By the way If you know how to deal with hieratic extraction in calibre I can switch to calibre since I just got the rule file for it.

Thank you so much.

Mo

 

[erikl]

... ERROR The fifth parameter must specify the substrate pin or nil in the mosDevice command.

As I'd already assumed, the Assura extract file syntax has changed meanwhile. At least the warnings tell you exactly what you have to change.

By the way If you know how to deal with hierarchic extraction in calibre I can switch to calibre since I just got the rule file for it.

Sorry, can't help here. Hope somebody else can tell you!

 

[nasroulm]

So I was able to run the LVS after modifying the LVSinclude.rsf file to take care of those mosDevice commands.
It look like that it can extract the schematic in the cell level (see the attached figure for the Schematic VNL) but unfortunately it can't extract my layout (see the attached figure for the Layout). [Schematic VNL.png] [L][Layout VNL.png][/img]

Thank you

 

[erikl]

It looks like that it can extract the schematic in the cell level (see the attached figure for the Schematic VNL) but unfortunately it can't extract my layout (see the attached figure for the Layout). [Schematic VNL.png] [Layout VNL.png]

Perhaps you used the wrong order in the schematic stop list? The layout extraction cannot go deeper than to the abstracts of your standard cells. In order to get comparable netlists, you must limit the schematic extraction to the same hierarchical level, i.e. it must stop before the symbols and not dive into their schematics. To achieve this correct stop in hierarchy level, the symbol view has to be the first one in the order of the schematic stop list, as I already suggested in my 1st answer to your thread from Sat, 27 Feb 2010 15:12 .